A field programmable bit-serial digital signal processor

The field programmable digital signal processor (FPDSP) architecture is intended to allow application specific DSP filtering at moderate sample rates where the ability to rapidly modify the filter characteristics can be used to an advantage. Applications that the FPDSP will be best suited for are rapid prototyping of filters, audio applications, and to evaluate the potential advantages of run-time reconfiguration. The system architecture is based on an input pipelined least significant bit first bit-serial two's complement arithmetic. It performs digital signal processing by using programmable bit-serial signal processing units and programmable interconnect. The bit-serial processing units implement simple arithmetic operations: summation, multiplication and division by powers of two, and multiplication by negative one. The programmable unit also has variable bit-delays to time-align bit-serial words and also generates the control signals for the arithmetic operations internally. By combining the functions of these programmable units, a 2nd order recursive filter has been built and tested to verify the functionality of the FPDSP.