{"title":"基于高度并行架构的H.264二维正/逆整数变换处理器","authors":"Ling Liu, Lin Qiu, Meng-tian Rong, Jiang Li","doi":"10.1109/IWSOC.2004.1319870","DOIUrl":null,"url":null,"abstract":"A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture\",\"authors\":\"Ling Liu, Lin Qiu, Meng-tian Rong, Jiang Li\",\"doi\":\"10.1109/IWSOC.2004.1319870\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.\",\"PeriodicalId\":306688,\"journal\":{\"name\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2004.1319870\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.1319870","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture
A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.
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