{"title":"可定制的嵌入式SoC平台架构","authors":"P. Nsame, Y. Savaria","doi":"10.1109/IWSOC.2004.1319898","DOIUrl":null,"url":null,"abstract":"In this paper, we present a general purpose and customizable IP platform, with hardware support for multiprocessors, multithreading and real-time applications. It integrates essential elements of a scalable SoC software and hardware architecture. The communication structure is based on virtual channels. As a result, the latencies across the software and hardware resources are significantly reduced. We use queues to communicate between functional units (or IP cores) in order to facilitate timing closure and verification.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A customizable embedded SoC platform architecture\",\"authors\":\"P. Nsame, Y. Savaria\",\"doi\":\"10.1109/IWSOC.2004.1319898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a general purpose and customizable IP platform, with hardware support for multiprocessors, multithreading and real-time applications. It integrates essential elements of a scalable SoC software and hardware architecture. The communication structure is based on virtual channels. As a result, the latencies across the software and hardware resources are significantly reduced. We use queues to communicate between functional units (or IP cores) in order to facilitate timing closure and verification.\",\"PeriodicalId\":306688,\"journal\":{\"name\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2004.1319898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.1319898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we present a general purpose and customizable IP platform, with hardware support for multiprocessors, multithreading and real-time applications. It integrates essential elements of a scalable SoC software and hardware architecture. The communication structure is based on virtual channels. As a result, the latencies across the software and hardware resources are significantly reduced. We use queues to communicate between functional units (or IP cores) in order to facilitate timing closure and verification.