2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献_第3页

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI 一种有效的测试方法，能够检测sram中的弱位:28nm FDSOI的案例研究

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064868

Nidhi Batra, Anil Kumar Gundu, M. Hashmi, G. Visweswaran, Anuj Grover

{"title":"An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI","authors":"Nidhi Batra, Anil Kumar Gundu, M. Hashmi, G. Visweswaran, Anuj Grover","doi":"10.1109/ISVDAT.2016.8064868","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064868","url":null,"abstract":"In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell primarily governs the performance with respect to yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post silicon. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. We present a case study for 64×64 SRAM in 28nm FDSOI technology. The proposed methodology targets high speed testing and lower test costs. It enables to perform the test at nominal operating voltage and room temperature. Suitable read stress is induced by boosting the Word Line (WL) voltage of the 6T SRAM cell. To validate the effectiveness of the test and find appropriate test stress we propose correlation methodology. With this test we could detect the weak cells possessing SNM upto 60mV across various process corners for stress voltage ranging from 1.14V to 1.16V. Moreover, it requires minimal area penalty and test time compared to standard tests.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116080527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power JSCAN:一种联合扫描DFT架构，可以最大限度地减少测试时间、模式体积和功耗

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064866

Jaynarayan T. Tudu

引用次数: 5

Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate 向后兼容MIL-STD-1553B模拟收发器升级为100 mb /s数据速率

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064845

P. Pendyala, V. Pasupureddi

引用次数: 0

New stable loadless 6T dual-port SRAM cell design 新的稳定的无负载6T双端口SRAM单元设计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064859

Antara Ganguly, Sangeeta Goyal, Sneha Bhatia, Anuj Grover

引用次数: 1

Design, integration and performance analysis of ΣΔ ADC for capacitive sensor interfacing 电容式传感器接口ΣΔ ADC的设计、集成及性能分析

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064892

P. Chatterjee, S. Kar, S. Sen

引用次数: 1

Energy-efficient reconfigurable framework for evaluating hybrid NoCs 评估混合noc的节能可重构框架

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064902

Raghav Kishore, H. Mondal, Sujay Deb

引用次数: 1

Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control Loop 高精度的可编程输出开关电容降压DC-DC变换器，采用Sigma-Delta反馈控制回路

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064883

Mahesh Zanwar, S. Sen

{"title":"Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control Loop","authors":"Mahesh Zanwar, S. Sen","doi":"10.1109/ISVDAT.2016.8064883","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064883","url":null,"abstract":"This paper describes the CMOS implementation of variable output voltage, multiphase switched capacitor step-down DC-DC converter with a large number of target voltages using Sigma-Delta Feedback Control Loop. The number of target voltages generated using n-flying capacitors are of the order of 2n. Expressions for equivalent series resistance Req, conduction, switching power loss and efficiency are obtained and compared with the spice simulation results. The Sigma-Delta Feedback Control Loop is designed which automatically switch between various target voltages and simulated in Cadence Analog-Mixed Signal flow. The Sigma-Delta feedback controller has a very high gain at DC and hence gives higher accuracy as compared to alternative methods. The 3/4 step-down converter circuit is described and analyzed by varying switching frequency and load for different values of bottom plate parasitic capacitance. An efficiency of about 77.3% is achieved with 10% bottom plate parasitic capacitance for a load current of 135 uA and input voltage of 1.8 V at 2 MHz of switching frequency. The load regulation of 7.33 mV/mA and line regulation of 6.5 mV/V is achieved.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134363244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimal design flow of CMOS doubler-based rectifiers CMOS倍频整流器的优化设计流程

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064885

Soumik Sarkar, Gaurav Saini, Mahima Arrawatia, M. Baghini

引用次数: 0

Synthesis aware sample preparation techniques using random sample sets in DMFB 在DMFB中使用随机样品集的合成感知样品制备技术

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064872

P. Roy, S. Chakraborty, H. Rahaman

{"title":"Synthesis aware sample preparation techniques using random sample sets in DMFB","authors":"P. Roy, S. Chakraborty, H. Rahaman","doi":"10.1109/ISVDAT.2016.8064872","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064872","url":null,"abstract":"Digital Microfluidic Biochips in recent years have emerged as a major feasible alternative platform for droplet based microfluidic operations within a miniaturized substrate. These devices find applications in the areas involving medical diagnostics, biochemical analysis and environmental toxicity monitoring issues. Formation of the sequencing graph for sample preparation followed by architecture level synthesis is the initial primary procedure for design automation of DMFBs. In this paper we proposed a technique for sample preparation using base solutions for a given random set of samples. The technique is developed to be synthesis aware in order to enable efficient use of resources in terms of modules for pipelined synthesis. The advantages of the proposed method is i) optimal resource utilization in terms of number of modules and samples and ii) efficient enhancement in overall execution time for the bioassay. The simulation is carried out with a given set of random samples as well as with a specified set of samples with Gaussian distribution. The results show encouraging improvements in i) number of sample utilizations, ii)number of mix-split operations iii)the formation of the number of waste droplets and iv) the actual number of modules used for execution of the overall bioassay.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A method to design a comparator for sampled data processing applications 一种用于采样数据处理应用的比较器设计方法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064863

Rama Prasad Acharya, Abir J. Mondal, A. Majumder

{"title":"A method to design a comparator for sampled data processing applications","authors":"Rama Prasad Acharya, Abir J. Mondal, A. Majumder","doi":"10.1109/ISVDAT.2016.8064863","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064863","url":null,"abstract":"The performance of a comparator is significantly affected by the time taken to determine the unequal bit location so as to decide greater than, less than and equal to condition. Consequently, the delay will increase with the number of bits of a comparator. The reduction in delay so as to improve performance can be achieved with the introduction of multilevel look-ahead circuit. In this work, a unique architecture of comparator with look-ahead circuit is introduced to reduce the worst case delay and to improve the overall performance. First, a multilevel look-ahead circuit is described to reduce the critical path delay effectively. Secondly, the realization of the comparator and multilevel look-ahead circuit using domino logic significantly reduces the complexity of the entire architecture. At first, a 4-bit unit cell is designed using domino logic. Thereafter, an 8-bit macro is realized using the unit cell. Further, 16-bit, 32-bit and 64-bit circuits are developed using the proposed 8-bit macro and multilevel look-ahead circuit. Simulation results show that the proposed 64-bit circuit has improved power dissipation compared to existing architectures. Moreover, the worst case delay has reduced significantly and the entire operation can be performed in a single clock cycle.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127821107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1