A method to design a comparator for sampled data processing applications

Rama Prasad Acharya, Abir J. Mondal, A. Majumder
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引用次数: 1

Abstract

The performance of a comparator is significantly affected by the time taken to determine the unequal bit location so as to decide greater than, less than and equal to condition. Consequently, the delay will increase with the number of bits of a comparator. The reduction in delay so as to improve performance can be achieved with the introduction of multilevel look-ahead circuit. In this work, a unique architecture of comparator with look-ahead circuit is introduced to reduce the worst case delay and to improve the overall performance. First, a multilevel look-ahead circuit is described to reduce the critical path delay effectively. Secondly, the realization of the comparator and multilevel look-ahead circuit using domino logic significantly reduces the complexity of the entire architecture. At first, a 4-bit unit cell is designed using domino logic. Thereafter, an 8-bit macro is realized using the unit cell. Further, 16-bit, 32-bit and 64-bit circuits are developed using the proposed 8-bit macro and multilevel look-ahead circuit. Simulation results show that the proposed 64-bit circuit has improved power dissipation compared to existing architectures. Moreover, the worst case delay has reduced significantly and the entire operation can be performed in a single clock cycle.
一种用于采样数据处理应用的比较器设计方法
为了确定大于、小于、等于条件而确定不相等位位置所花费的时间对比较器的性能有很大的影响。因此,延迟将随着比较器的位数增加而增加。通过引入多电平预判电路来降低延迟,从而提高性能。为了减少最坏情况下的延迟,提高比较器的整体性能,本文提出了一种独特的带前瞻性电路的比较器结构。首先,提出了一种多电平预判电路,有效地降低了关键路径的延迟。其次,采用多米诺骨牌逻辑实现比较器和多层预判电路,大大降低了整个体系结构的复杂度。首先,使用domino逻辑设计一个4位单元格。然后,使用单元格实现一个8位宏。此外,16位,32位和64位电路被开发使用所提出的8位宏和多层前瞻性电路。仿真结果表明,与现有架构相比,所提出的64位电路具有更好的功耗。此外,最坏情况下的延迟大大减少,整个操作可以在一个时钟周期内完成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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