2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献

A high speed low voltage latch type sense amplifier for non-volatile memory 一种用于非易失性存储器的高速低压锁存器型感测放大器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-24 DOI: 10.1109/ISVDAT.2016.8064841

Disha Arora, Anil Kumar Gundu, M. Hashmi

引用次数: 6

Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method 用Adomian分解法分析动态锁存器的再生时间常数

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-24 DOI: 10.1109/ISVDAT.2016.8064860

A. Purushothaman

{"title":"Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method","authors":"A. Purushothaman","doi":"10.1109/ISVDAT.2016.8064860","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064860","url":null,"abstract":"This paper presents Adomian Decomposition based analysis of regeneration time constant of CMOS dynamic cross-coupled latch. A CMOS dynamic cross-coupled latch, which is a nonlinear system, is typically analyzed by linearizing it around an operating point to arrive at regeneration time constant. However, the time domain behavior obtained using the linear analysis deviates from the actual behavior of the latch. Thus, circuit simulators like SPICE and Spectre solve the nonlinear differential equations numerically to obtain the time domain behavior. These numerical solutions neither give a closed form expression of the regeneration time-constant nor do they give an expression of time domain behavior in closed form. Adomian Decomposition Method (ADM), however, can be used to obtain the complete time-domain behavior and the regeneration time-constant. ADM expresses the solution of a nonlinear differential equation in a manner similar to Taylor series approximation of a polynomial. The paper first introduces the concept of ADM and then applies it to RC linear circuits. c. Simulations show good agreement between Cadence based and ADM based time domain behavior.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134474031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

New technique to improve transient response of LDO regulators without an off-chip capacitor 无片外电容改善LDO稳压器瞬态响应的新技术

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-24 DOI: 10.1109/ISVDAT.2016.8064847

C. Parikh, Gopal Agarwal

引用次数: 2

Synthesis of scheduler automata guaranteeing stability and reliability of embedded control systems 调度自动机的综合，保证嵌入式控制系统的稳定性和可靠性

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-24 DOI: 10.1109/ISVDAT.2016.8064856

S. Ghosh, Akash Mondal, Souradeep Dutta, Aritra Hazra, Soumyajit Dey

引用次数: 2

Frequency domain analysis of on-chip power distribution network 片上配电网的频域分析

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-24 DOI: 10.1109/ISVDAT.2016.8064853

Shipra Batra, Pankhuri Singh, S. Kaushik, M. Hashmi

引用次数: 1

An efficient reversible cryptographic circuit design 一种高效的可逆密码电路设计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064874

Bikromadittya Mondal, Kushal Dey, Susanta Chakraborty

引用次数: 0

A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness 一个Pre-RTL地板规划工具，用于自动CMP设计空间探索，具有热意识

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064876

G. Harsha, Praveen Kumar, Sujay Deb

{"title":"A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness","authors":"G. Harsha, Praveen Kumar, Sujay Deb","doi":"10.1109/ISVDAT.2016.8064876","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064876","url":null,"abstract":"Chip Multiprocessor (CMP) and System-on-Chip (SoC) designs have a large number of modules with billions of transistors embedded on a single die. While they offer very high performance, they also increase the design complexity and pose many challenges with one of them being floor-planning and placement. Floor-planning process is affected by and in turn effects physical characteristics, wire length, propagation delay between modules, power and thermal density of the chip. Floor-planning at backend generally takes considerable amount of runtime. With large design space of CMP/SoC designs, it is not possible to explore multiple options or rerun the process in case of discrepancies. In this work, we propose and develop a pre-RTL tool framework that performs floor-planning analysis at early stages of development. The primary goal is to perform floor-plan analysis using abstract description of a design. The tool explores multiple layout options for a design and provide insights into different physical aspects like area, relative position of IPs, thermal and power performance. Since detailed physical information is not required at early stages, it allows us to explore the vast design space of SoCs. The tool is written in python and is based on simulated annealing algorithm which is adapted to the problem's context. We demonstrate the utility and robustness of the tool in providing multiple layout options with different user specifications.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design of coherence verification unit for CMPs realizing dragon protocol 实现龙协议的cmp相干验证单元设计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064850

B. Chakraborty, M. Dalui, B. Sikdar

引用次数: 3

A FSM based approach for efficient implementation of K-means algorithm 基于FSM的K-means算法高效实现方法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064848

Rahul Ratnakumar, S. Nanda

{"title":"A FSM based approach for efficient implementation of K-means algorithm","authors":"Rahul Ratnakumar, S. Nanda","doi":"10.1109/ISVDAT.2016.8064848","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064848","url":null,"abstract":"After Fifty years of it's existence the K-means clustering is still popular among researchers due to lower computational complexity. Real time embedded applications require hardwiring of unsupervised learning algorithms like K-means within System-on-Chip for prompt processing in applications like image segmentation, pattern classification, speech recognition etc. This requirement is a must while analyzing Big Datasets. In this manuscript a FSM based architecture is developed for the efficient implementation of K-means algorithm. The proposed architecture has lower computational requirement due to the introduction of concepts like simplified Convergence Checker as well as Fibonacci linear feedback shift register for centroid initialization. To reduce hardware further, Manhattan distance is used as the distance metric instead of the conventional Euclidean distance. Benchmark IRIS flower dataset is used for testing the clustering performance of the proposed architecture. Results obtained after synthesis in Xilinx FPGA Artix7, reveals that the hardware performance is better than previous works, with respect to power (82mW), number of gates, area etc. and has good system clock frequency of 162MHz (6.1592ns), without using any DSP Blocks.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116137585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A robust 8T FinFET SRAM cell with improved stability for low voltage applications 一个强大的8T FinFET SRAM单元，具有提高的稳定性，适用于低电压应用

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064858

C. Kushwah, D. Dwivedi, N. Sathisha, Krishnan S. Rengarajan

引用次数: 0