A robust 8T FinFET SRAM cell with improved stability for low voltage applications

Abstract

As we move in sub-nanometer range, we have to deal with its darker side with problems like short channel effects. The yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of small size memory cells, process variations in cells leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this paper, we have used reverse bitlines feedback control (RBLFC) and data isolation enhanced read (DIER) techniques which results in 7 sigma yield at system level. The novel structure of proposed 8T cell gives 6% higher hold static noise margin (HSNM) and 66% higher write static noise margin (WSNM) as compared to conventional 6T cell. Proposed 8T cell allows 29% faster write operation as compared to 6T with 20% lower leakage power.