2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献_第2页

A constraint driven technique for MOS amplifier design MOS放大器设计中的约束驱动技术

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064882

Paromita Bhattacharjee, Abir J. Mondal, A. Majumder

{"title":"A constraint driven technique for MOS amplifier design","authors":"Paromita Bhattacharjee, Abir J. Mondal, A. Majumder","doi":"10.1109/ISVDAT.2016.8064882","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064882","url":null,"abstract":"The performance of a single stage amplifier when expressed as a function of designable and technology related parameters can be improved by adjusting the component values and transistor dimensions. In the process to optimize the performance, the corresponding parameters can be expressed in terms of objective function and constraints so as to graphically form a polytope type feasible region. Thereafter, simplex method and interior point based method are used to find an optimal value by traversing through each of the corner point and interior of the polytope formed. Consequently, the amplifier design problem can be realized as a special form of optimization problem called Non Linear Programming (NLP), for which efficient global optimization methods have been developed. The present method yields completely an automated synthesis of single stage amplifiers directly from the specifications. In this paper, the proposed method is first described showing in detail the formulation of the design problem as NLP for a specific amplifier circuit and then applied to a wide variety of amplifier architectures. The optimal trade-off curves related to performance measures such as small signal gain(Av), unity gain frequency(UGF), slew rate(SR) and power are derived so as to observe the corresponding dependencies.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123163174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High performance bit-sliced pipelined comparator tree for FPGAs 用于fpga的高性能位切片流水线比较器树

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064843

Ayan Palchaudhuri, A. Dhar

{"title":"High performance bit-sliced pipelined comparator tree for FPGAs","authors":"Ayan Palchaudhuri, A. Dhar","doi":"10.1109/ISVDAT.2016.8064843","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064843","url":null,"abstract":"In this paper, we have implemented high performance FPGA based pipelined tree architectures for a combined unsigned and two's complement comparator, and an equality comparator which checks whether the sum of two numbers is equal to a third number. The comparator architectures deviate from the combined Look-Up Table (LUT) and carry chain based implementation which is inferred by the Xilinx Synthesis Tool. The feasibility of this work comes from the increased device density offered by the 6 and 7 series FPGA architectures from Xilinx, where every dual output function derived from a single LUT can be registered using a flip-flop present within the same slice as that of the LUT. Pipelining a tree based architecture completely eliminates the requirement of any synchronization registers for balancing the arrival time of the inputs and outputs, and their associated placement and routing challenges. The architecture has been realized through primitive instantiation of the logic elements to ensure packing of the dual output functions into a single LUT wherever possible, and the placement of the LUTs on the FPGA fabric using appropriate placement constraints. Implementation results clearly reveal the superiority of our design paradigm over behavioral style of modeling, where our proposed architectures consume less area, and operates at a higher speed in comparison to an identical circuit realized using behavioral descriptions.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127056370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier SRAM感测放大器时延分析的可变性和可靠性感知代理模型

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064839

S. Khandelwal, J. Meena, L. Garg, D. Boolchandani

{"title":"Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier","authors":"S. Khandelwal, J. Meena, L. Garg, D. Boolchandani","doi":"10.1109/ISVDAT.2016.8064839","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064839","url":null,"abstract":"Variability and reliability have become major threats in nano scale era. Both leads to variation in transistor parameters that eventually affect the performance parameters. One of the failure mechanism is Bias Temperature Instability (BTI) which impacts mobility and threshold voltage (Vth) of the transistor. This paper investigates the impact of BTI on SRAM sense amplifier at different process corners along with variability effect in 45nm technology. The results depict that, impact of Positive BTI (PBTI) is less than Negative BTI (NBTI) on sensing delay of sense amplifier. Moreover across all process corners sensing delay increases as supply voltage (Vbd) decreases and temperature increases. A surrogate model has been developed by using support vector machine (SVM) for variability and reliability analysis of sensing delay. Adaptive learning is used in order to develop the model with less number of samples which attributes to less run time. Evaluation of single sample of sensing delay requires 0.077ms and 0.081ms for read 0 and read 1 respectively. Correlation coefficient has been obtained between HSPICE and SVM in order to validate the model. The values of correlation coefficients are 0.9996 and 0.9997 for read 0 and read 1 respectively.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124442358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guided multilevel approximation of less significant bits for power reduction 用于降低功率的低重要位的制导多电平近似

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064879

D. Celia, N. Chandrachoodan

引用次数: 0

On determination of instantaneous peak and cycle peak switching using ILP 用ILP法确定瞬时峰值和周期峰值切换

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064881

Rohini Gulve, N. Hage, Jaynarayan T. Tudu

{"title":"On determination of instantaneous peak and cycle peak switching using ILP","authors":"Rohini Gulve, N. Hage, Jaynarayan T. Tudu","doi":"10.1109/ISVDAT.2016.8064881","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064881","url":null,"abstract":"Power has becomes one of the crucial parameter while designing a SOC ICs. Power analysis of a circuit is important for reliability check, better design of power distribution network, packaging decisions and to solve power issues during test. High switching at a time demands high instantaneous current from power supply network. Which gates experience Vdd drop leading to increase in delay of the circuit. Power consumed by circuit is proportional to switching activity at gate outputs and capacitance associated with it. Most of the previous work consider switching activity over entire clock period, however this is very pessimistic approach. All gates do not switch at the same time because of associated delays, thus peak switching occurring at an instant of time should be considered. In this paper we formulate an Integer Linear Programming for computing maximum transitions in the circuit at any instant time as well as during entire clock period. This method identifies a vector pair which provides the highest activity in the circuit. The proposed method captures the impact of glitches occurring during signal propagation. Our analysis shows that the maximum 75% of total gates can switch at any time instant and the maximum 625% of total gates can switch during clock period.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134361726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Guided shifting of test pattern to minimize test time in serial scan 引导转换测试模式，以减少串行扫描的测试时间

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064851

Jaynarayan T. Tudu, Satyadev Ahlawat

引用次数: 0

A strategy for fault tolerant reconfigurable Network-on-Chip design 一种容错可重构片上网络设计策略

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064893

Navonil Chatterjee, Priyajit Mukherjee, S. Chattopadhyay

引用次数: 4

EG0N: Portable in-situ energy measurement for low-power sensor devices EG0N:用于低功耗传感器设备的便携式原位能量测量

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064889

Nils Heitmann, Philipp H. Kindt, S. Chakraborty

{"title":"EG0N: Portable in-situ energy measurement for low-power sensor devices","authors":"Nils Heitmann, Philipp H. Kindt, S. Chakraborty","doi":"10.1109/ISVDAT.2016.8064889","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064889","url":null,"abstract":"For assessing the energy consumption of an embedded system, typically measurements on a shunting resistor are conducted in a laboratory environment. While such measurements can be easily performed with high precision for stationary setups, obtaining data on the energy-consumption of mobile devices, such as body-worn electronics (wearables) is a significantly more challenging task, since the power consumption depends on the behavior of the user. For example, consider an activity sensor which transmits the detected activity type (e.g., walking, running, resting) wirelessly to a smartphone whenever the activity changes. Clearly, more current is drawn for the transmission whenever the activity needs to be updated. Connecting the device with long wires to a stationary measurement platform distorts the results and restricts the motion of the user. Therefore, the measurement platform needs to be mobile itself to measure in-situ. This imposes multiple challenges on such a system, e.g., the limited power budget for obtaining samples of the current consumption and the need for miniaturized electronics. In this paper, we propose EG0N, a mobile current measurement platform for wearables. While addressing the mentioned challenges, it supports useful advanced features, such as collaborative, context-aware measurements on the device-under-test (DUT).","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122910143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology 基于180nm MM CMOS技术的失配不敏感可重构离散时间生物信号调理电路

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064907

Priyanka Kimtee, D. Das, M. Baghini

{"title":"A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology","authors":"Priyanka Kimtee, D. Das, M. Baghini","doi":"10.1109/ISVDAT.2016.8064907","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064907","url":null,"abstract":"This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact on the precision of the signal sensing. Moreover fully differential circuit is very sensitive to capacitor mismatch leading to degradation of CMRR. To overcome this limitation, a new circuit configuration is presented, which uses the concept of error averaging. As a result, the circuit achieves minimum CMRR of 90 dB for frequencies in the range of 40–60 Hz, even in the presence of 0.1% capacitor mismatch, along with process and temperature variations. Simulation results show the worst case relative output error of ± 0.57% and ± 0.9% with DC and time varying input common mode voltage respectively. Also, the circuit achieves 10-bit resolution, even with capacitor mismatch and input common mode variations.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129403775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Performance analysis of temperature dependent GNR interconnect 温度相关GNR互连的性能分析

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064864

Waikhom Mona Chanu, Vikash Prasad, Debaprasad Das

引用次数: 2