High performance bit-sliced pipelined comparator tree for FPGAs

Abstract

In this paper, we have implemented high performance FPGA based pipelined tree architectures for a combined unsigned and two's complement comparator, and an equality comparator which checks whether the sum of two numbers is equal to a third number. The comparator architectures deviate from the combined Look-Up Table (LUT) and carry chain based implementation which is inferred by the Xilinx Synthesis Tool. The feasibility of this work comes from the increased device density offered by the 6 and 7 series FPGA architectures from Xilinx, where every dual output function derived from a single LUT can be registered using a flip-flop present within the same slice as that of the LUT. Pipelining a tree based architecture completely eliminates the requirement of any synchronization registers for balancing the arrival time of the inputs and outputs, and their associated placement and routing challenges. The architecture has been realized through primitive instantiation of the logic elements to ensure packing of the dual output functions into a single LUT wherever possible, and the placement of the LUTs on the FPGA fabric using appropriate placement constraints. Implementation results clearly reveal the superiority of our design paradigm over behavioral style of modeling, where our proposed architectures consume less area, and operates at a higher speed in comparison to an identical circuit realized using behavioral descriptions.