A strategy for fault tolerant reconfigurable Network-on-Chip design

Abstract

In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with the faulty routers by dynamically reconfiguring itself and updating the routing table associated with individual routers.