{"title":"基于180nm MM CMOS技术的失配不敏感可重构离散时间生物信号调理电路","authors":"Priyanka Kimtee, D. Das, M. Baghini","doi":"10.1109/ISVDAT.2016.8064907","DOIUrl":null,"url":null,"abstract":"This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact on the precision of the signal sensing. Moreover fully differential circuit is very sensitive to capacitor mismatch leading to degradation of CMRR. To overcome this limitation, a new circuit configuration is presented, which uses the concept of error averaging. As a result, the circuit achieves minimum CMRR of 90 dB for frequencies in the range of 40–60 Hz, even in the presence of 0.1% capacitor mismatch, along with process and temperature variations. Simulation results show the worst case relative output error of ± 0.57% and ± 0.9% with DC and time varying input common mode voltage respectively. Also, the circuit achieves 10-bit resolution, even with capacitor mismatch and input common mode variations.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology\",\"authors\":\"Priyanka Kimtee, D. Das, M. Baghini\",\"doi\":\"10.1109/ISVDAT.2016.8064907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact on the precision of the signal sensing. Moreover fully differential circuit is very sensitive to capacitor mismatch leading to degradation of CMRR. To overcome this limitation, a new circuit configuration is presented, which uses the concept of error averaging. As a result, the circuit achieves minimum CMRR of 90 dB for frequencies in the range of 40–60 Hz, even in the presence of 0.1% capacitor mismatch, along with process and temperature variations. Simulation results show the worst case relative output error of ± 0.57% and ± 0.9% with DC and time varying input common mode voltage respectively. Also, the circuit achieves 10-bit resolution, even with capacitor mismatch and input common mode variations.\",\"PeriodicalId\":301815,\"journal\":{\"name\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVDAT.2016.8064907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 20th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2016.8064907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology
This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact on the precision of the signal sensing. Moreover fully differential circuit is very sensitive to capacitor mismatch leading to degradation of CMRR. To overcome this limitation, a new circuit configuration is presented, which uses the concept of error averaging. As a result, the circuit achieves minimum CMRR of 90 dB for frequencies in the range of 40–60 Hz, even in the presence of 0.1% capacitor mismatch, along with process and temperature variations. Simulation results show the worst case relative output error of ± 0.57% and ± 0.9% with DC and time varying input common mode voltage respectively. Also, the circuit achieves 10-bit resolution, even with capacitor mismatch and input common mode variations.