2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献_第7页

An area and performance aware ECG encoder design for wireless healthcare services 面向无线医疗服务的区域和性能感知心电编码器设计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064861

Bharat Garg, Sameer Yadav, G. K. Sharma

{"title":"An area and performance aware ECG encoder design for wireless healthcare services","authors":"Bharat Garg, Sameer Yadav, G. K. Sharma","doi":"10.1109/ISVDAT.2016.8064861","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064861","url":null,"abstract":"Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) signal which is used to diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder is the critical requirement in wireless health care services. This paper presents an area efficient and high performance lossless ECG encoder that utilizes a single stage Huffman table to provide compressed ECG data. In the proposed ECG encoder architecture, low range of ECG data is encoded via small Huffman table whereas out of range data is segmented into upper and lower parts. These upper and lower parts are encoded by the same Huffman table in the two consecutive clock cycles. This architecture is implemented in MATLAB and simulated with MIT-BIH Arrhythmia database. The simulation results of the proposed ECG encoder show 72.87% more compression over the existing ECG encoder. To evaluate the hardware efficiency, the encoder is implemented in Verilog and synthesized with Synopsys Design Compiler using 90nm PDK. The results show that proposed encoder requires 12.11% less area and provides 2.1X improved performance over the existing encoder.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA 基于密度梯度量子修正的三角形TG体finfet性能优化

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064854

A. Gaurav, S. S. Gill, Navneet Kaur, M. Rattan

引用次数: 9

A low-cost energy efficient image scaling processor for multimedia applications 用于多媒体应用的低成本节能图像缩放处理器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064888

Bharat Garg, V. N. S. K. C. Goteti, G. K. Sharma

引用次数: 12

A high CMRR, high resolution bio-ASIC for ECG signals 一种用于心电信号的高CMRR，高分辨率生物asic

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064890

K. Garje, Shravan Kumar, A. Tripathi, Gillela Maruthi, Madhava Kumar

引用次数: 3

On minimization of test power through modified scan flip-flop 改进扫描触发器使测试功率最小化的研究

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064878

Satyadev Ahlawat, Jaynarayan T. Tudu

引用次数: 5

SAT: A new application mapping method for power optimization in 2D — NoC 一种新的2D - NoC电源优化应用映射方法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064880

Aravindhan Alagarsamy, Lakshminaraynan Gopalakrishnan

引用次数: 11

FSK demodulator and FPGA based BER measurement system for low IF receivers 基于FSK解调器和FPGA的低中频接收机误码率测量系统

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064901

K. N. Sankar, Abhishek Srivastava, Baibhab Chatterjee, K. K. Rakesh, M. Baghini

引用次数: 1

BDD based synthesis technique for design of high-speed memristor based circuits 基于BDD的高速忆阻电路设计综合技术

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064842

Anindita Chakraborty, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman

{"title":"BDD based synthesis technique for design of high-speed memristor based circuits","authors":"Anindita Chakraborty, Rakesh Das, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/ISVDAT.2016.8064842","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064842","url":null,"abstract":"Recently, a passive device — memristor has received wide attention in nano-scale design due to its applications in the area of nanoelectronic memory design, neuromorphic computing and logic design. This passive element is non-volatile in nature and has dual properties of memory and resistor. In recent time, the application of this device in designing high speed logic circuits has now opened a new research domain in nano-scale design. This work presents an efficient design technique implementing logic functions using memristor. The proposed design methodology not only speed-up the response time of the circuits but can also deal with functions with larger input size (beyond 100 variables). Our entire design scheme is divided in two phases. In the first phase, we use Binary Decision Diagrams (BDDs) to represent input logic functions and in second phase, a technology mapping is performed that generates memristor based circuits corresponding to this BDD graphs. Comparative analysis with existing works is given and we find that our design steadily improves the average performance of circuits.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127956799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation 一个统一的Verilog-A紧凑模型的横向硅纳米线(NW)场效应管集成寄生电路仿真

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064852

Om. Prakash, S. Maheshwaram, Mohit Sharma, B. Anand, A. Saxena, S. Manhas

{"title":"A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation","authors":"Om. Prakash, S. Maheshwaram, Mohit Sharma, B. Anand, A. Saxena, S. Manhas","doi":"10.1109/ISVDAT.2016.8064852","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064852","url":null,"abstract":"This paper presents a unified Verilog-A compact model for lateral silicon nanowire field effect transistor (SiNW FET). The model incorporates all nanoscale effects including short channel effects, velocity saturation, mobility degradation, and quantization. Importantly, the model includes geometry dependent, TCAD calibrated, scalable parasitic capacitances and parasitic resistance models, which are dominant at highly scaled dimension. The model is well calibrated to generate the TCAD I-V and C-V characteristics for single and multiwire long, short channel devices. In addition, the model also reproduces I-V characteristics of the reported fabricated devices by different groups to a good accuracy, which underscores the accuracy of the model. Further using the compact model, the static and dynamic analysis of CMOS inverter with 15nm gate length is presented, which match well with TCAD simulations. Using this model the impact of device parasitic on circuit performance is studied by varying device extension length. The model is able to well predict the parasitic components for circuit performance, and is an important tool for design of NW based analog and digital circuits such as differential amplifier, current mirror, cell library and SRAM. The developed model is highly time efficient than TCAD simulator for NW based circuit simulations.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127234318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Tutorials in VDAT 2016 VDAT 2016教程

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 1900-01-01 DOI: 10.1109/isvdat.2016.8064838

引用次数: 0