{"title":"面向无线医疗服务的区域和性能感知心电编码器设计","authors":"Bharat Garg, Sameer Yadav, G. K. Sharma","doi":"10.1109/ISVDAT.2016.8064861","DOIUrl":null,"url":null,"abstract":"Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) signal which is used to diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder is the critical requirement in wireless health care services. This paper presents an area efficient and high performance lossless ECG encoder that utilizes a single stage Huffman table to provide compressed ECG data. In the proposed ECG encoder architecture, low range of ECG data is encoded via small Huffman table whereas out of range data is segmented into upper and lower parts. These upper and lower parts are encoded by the same Huffman table in the two consecutive clock cycles. This architecture is implemented in MATLAB and simulated with MIT-BIH Arrhythmia database. The simulation results of the proposed ECG encoder show 72.87% more compression over the existing ECG encoder. To evaluate the hardware efficiency, the encoder is implemented in Verilog and synthesized with Synopsys Design Compiler using 90nm PDK. The results show that proposed encoder requires 12.11% less area and provides 2.1X improved performance over the existing encoder.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An area and performance aware ECG encoder design for wireless healthcare services\",\"authors\":\"Bharat Garg, Sameer Yadav, G. K. Sharma\",\"doi\":\"10.1109/ISVDAT.2016.8064861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) signal which is used to diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder is the critical requirement in wireless health care services. This paper presents an area efficient and high performance lossless ECG encoder that utilizes a single stage Huffman table to provide compressed ECG data. In the proposed ECG encoder architecture, low range of ECG data is encoded via small Huffman table whereas out of range data is segmented into upper and lower parts. These upper and lower parts are encoded by the same Huffman table in the two consecutive clock cycles. This architecture is implemented in MATLAB and simulated with MIT-BIH Arrhythmia database. The simulation results of the proposed ECG encoder show 72.87% more compression over the existing ECG encoder. To evaluate the hardware efficiency, the encoder is implemented in Verilog and synthesized with Synopsys Design Compiler using 90nm PDK. The results show that proposed encoder requires 12.11% less area and provides 2.1X improved performance over the existing encoder.\",\"PeriodicalId\":301815,\"journal\":{\"name\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVDAT.2016.8064861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 20th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2016.8064861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An area and performance aware ECG encoder design for wireless healthcare services
Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) signal which is used to diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder is the critical requirement in wireless health care services. This paper presents an area efficient and high performance lossless ECG encoder that utilizes a single stage Huffman table to provide compressed ECG data. In the proposed ECG encoder architecture, low range of ECG data is encoded via small Huffman table whereas out of range data is segmented into upper and lower parts. These upper and lower parts are encoded by the same Huffman table in the two consecutive clock cycles. This architecture is implemented in MATLAB and simulated with MIT-BIH Arrhythmia database. The simulation results of the proposed ECG encoder show 72.87% more compression over the existing ECG encoder. To evaluate the hardware efficiency, the encoder is implemented in Verilog and synthesized with Synopsys Design Compiler using 90nm PDK. The results show that proposed encoder requires 12.11% less area and provides 2.1X improved performance over the existing encoder.