K. Garje, Shravan Kumar, A. Tripathi, Gillela Maruthi, Madhava Kumar
{"title":"一种用于心电信号的高CMRR，高分辨率生物asic","authors":"K. Garje, Shravan Kumar, A. Tripathi, Gillela Maruthi, Madhava Kumar","doi":"10.1109/ISVDAT.2016.8064890","DOIUrl":null,"url":null,"abstract":"A High CMRR, High-resolution signal processing bioASIC circuit for wireless and wearable systems is presented. The chip consists of High CMRR Instrumentation Amplifier (IA) integrated with high accuracy pipeline ADC. The bio-ASIC front-end is built using current balance IA circuit followed by high pass and low pass filters. A High resolution, wide dynamic range, integrated Pipeline ADC allows input swing of ±1V. The ASIC is fabricated in 0.13μm CMOS process technology. The measured CMRR and integrated input referred noise of the circuit is 176dB at 150Hz and 4.5μν over the bandwidth of 0.1–150Hz. The Input Common Mode Range (ICMR) is 0–1.65V and the dynamic range is ±5mV. The ADC offers ENOB of 12.8 at 6 MSPS sampling speed & ± 0.75LSB of differential nonlinearity. The power consumption of the Instrumentation amplifier circuit is 33μW with a 3.3V supply.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A high CMRR, high resolution bio-ASIC for ECG signals\",\"authors\":\"K. Garje, Shravan Kumar, A. Tripathi, Gillela Maruthi, Madhava Kumar\",\"doi\":\"10.1109/ISVDAT.2016.8064890\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A High CMRR, High-resolution signal processing bioASIC circuit for wireless and wearable systems is presented. The chip consists of High CMRR Instrumentation Amplifier (IA) integrated with high accuracy pipeline ADC. The bio-ASIC front-end is built using current balance IA circuit followed by high pass and low pass filters. A High resolution, wide dynamic range, integrated Pipeline ADC allows input swing of ±1V. The ASIC is fabricated in 0.13μm CMOS process technology. The measured CMRR and integrated input referred noise of the circuit is 176dB at 150Hz and 4.5μν over the bandwidth of 0.1–150Hz. The Input Common Mode Range (ICMR) is 0–1.65V and the dynamic range is ±5mV. The ADC offers ENOB of 12.8 at 6 MSPS sampling speed & ± 0.75LSB of differential nonlinearity. The power consumption of the Instrumentation amplifier circuit is 33μW with a 3.3V supply.\",\"PeriodicalId\":301815,\"journal\":{\"name\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVDAT.2016.8064890\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 20th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2016.8064890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high CMRR, high resolution bio-ASIC for ECG signals
A High CMRR, High-resolution signal processing bioASIC circuit for wireless and wearable systems is presented. The chip consists of High CMRR Instrumentation Amplifier (IA) integrated with high accuracy pipeline ADC. The bio-ASIC front-end is built using current balance IA circuit followed by high pass and low pass filters. A High resolution, wide dynamic range, integrated Pipeline ADC allows input swing of ±1V. The ASIC is fabricated in 0.13μm CMOS process technology. The measured CMRR and integrated input referred noise of the circuit is 176dB at 150Hz and 4.5μν over the bandwidth of 0.1–150Hz. The Input Common Mode Range (ICMR) is 0–1.65V and the dynamic range is ±5mV. The ADC offers ENOB of 12.8 at 6 MSPS sampling speed & ± 0.75LSB of differential nonlinearity. The power consumption of the Instrumentation amplifier circuit is 33μW with a 3.3V supply.
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