2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献_第6页

An effective and efficient algorithm to analyse and debug clock propagation issues 一种分析和调试时钟传播问题的有效算法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064849

Pawan Sehgal, Aditi Sharma, A. Mishra, R. Ramanujam, Sujay Deb

{"title":"An effective and efficient algorithm to analyse and debug clock propagation issues","authors":"Pawan Sehgal, Aditi Sharma, A. Mishra, R. Ramanujam, Sujay Deb","doi":"10.1109/ISVDAT.2016.8064849","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064849","url":null,"abstract":"The evolution of deep submicron (DSM) era has resulted in rapid shrinking of the System-on-Chip (SoC) simultaneously with the exponential increase in the design complexity. Larger designs require numerous Intellectual Properties (IPs) composed of millions of combinational and sequential cells to serve the purpose which further require an extensive web of complex clock tree architecture for effective functionality. But with the increase in complexity, it is becoming more and more difficult to keep track about the clock signal effectively reaching to each intended sequential leaf cell. Clock signal, if gets blocked, can hamper the functionality of that particular IP and the effect, in essence, can further ripples down to broken functionality of the complete design. It is therefore imperative to thoroughly check the design for the locations where clock signal is unavailable in early stages of design implementations. This paper provides an algorithm in form of prototype debugger tool which aims at identifying the root cause of no clock signal reaching the clock pin of sequential cell in single iteration. It moves a step further by looking ahead and detecting all the possible potential blocking reasons, apart from the actual ones within a given clock path to a sequential cell in the same iteration. Experimental results on set top box chip show the effectiveness and the efficiency of this method by capturing all the actual and additional probable clock blocking reasons in a single step.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding 利用偏移二进制编码高效实现并发前瞻决策反馈均衡器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064862

Mohd. Tasleem Khan, S. Ahamed, A. Chatterjee

{"title":"Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding","authors":"Mohd. Tasleem Khan, S. Ahamed, A. Chatterjee","doi":"10.1109/ISVDAT.2016.8064862","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064862","url":null,"abstract":"In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of parallelization. However, the hardware complexity of adders and multipliers rises quadratically with parallelization factor. In our proposed technique, we have used look-up table (LUT) and shift-accumulate block as per DA requirement. In order to reduce the access time of LUT, we employed OBC scheme which therefore improves the speed of filtering operation. Moreover, it also reduces the chip area for LUT based filter design. Furthermore, our design provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly. By doing so, the concurrent nature of look-ahead DFE is unaltered and can still be used for multi-gigabit applications. We have estimated hardware complexity and critical path of our design and compared with best existing schemes. Synthesis is performed in UMC 180 nm CMOS technology using cadence RTL compiler for the feedback filter length N = 4, 6 and 8. The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130097830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design methodology of closed loop MEMS capacitive accelerometers based on ΣΔ modulation technique 基于ΣΔ调制技术的闭环MEMS电容式加速度计设计方法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064884

P. Chatterjee, S. Kar, S. Sen

引用次数: 1

Switched-capacitor circuit simulator in Q-V domain including nonidealities 包括非理想性的Q-V域开关电容电路模拟器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064865

G. Muralidhar, Dinesh Ganesan, B. Kailath

{"title":"Switched-capacitor circuit simulator in Q-V domain including nonidealities","authors":"G. Muralidhar, Dinesh Ganesan, B. Kailath","doi":"10.1109/ISVDAT.2016.8064865","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064865","url":null,"abstract":"Circuit simulations need to be performed as a pre-manufacturing design strategy for checking and verifying design of electrical and electronic circuits and systems. Switched capacitor circuits belong to a class of circuits where signal processing is performed by charge redistribution among series of capacitors based on the configuration. In order to simulate the true characteristics of such circuits, the simulator should be capable of, formulating the circuit parameters based on charge redistribution rather than current-voltage relationship and, including non-idealities such as charge injection, parasitic capacitance effect, improper charge redistribution causing settling error etc. A switched capacitor circuit simulator addressing charge redistribution is presented in this paper. It works on the principle of quantifying all circuit parameters based on charge-voltage formulation which enables linearized approximation for nonlinear characteristics while evaluating the time response. The proposed simulator also incorporates nonideality of charge leakage and nonlinear capacitance. It permits piecewise constant and continuous inputs for evaluating the time response and employs numerical techniques such as Gauss elimination and LU factorization to solve equations. The linearized formulation enables shorter simulation time which otherwise requires many clock cycles and provides better convergence and accuracy. Three sample circuits are considered to validate the performance of the simulator. The entire simulator is developed in PYTHON environment taking SPICE type netlist as inputs.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125595414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards a dynamic associativity enabled write prediction based hybrid cache 实现基于动态关联的写预测混合缓存

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064870

Sukarn Agarwal, H. Kapoor

引用次数: 1

An efficient FPGA-based function profiler for embedded system applications 一个高效的基于fpga的嵌入式系统功能分析器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064857

Pavan Kumar Nadimpalli, S. Roy

{"title":"An efficient FPGA-based function profiler for embedded system applications","authors":"Pavan Kumar Nadimpalli, S. Roy","doi":"10.1109/ISVDAT.2016.8064857","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064857","url":null,"abstract":"Modern embedded systems are typically implemented using both programmable processors and application specific hardware in order to meet real time design goals, besides other metrics, such as, performance, area and cost. The availability of programmable processors and application specific hardware enables an application architect to partition the execution of the given application code (specified in some high-level language) optimally; so as to execute as large a portion of it, which is timing or performance non-critical, on the processor to lower implementation cost and the timing critical rest, in expensive application specific digital hardware, implemented either as an ASIC or programmed into a FPGA. Profiling tools enables this optimal partitioning by monitoring the execution of the application code running on a processor and capturing different characteristics of the program execution. One of the important aspect that needs to be profiled is the cost of executing functions or subroutines, in terms of both the computational cost, as well as, the communication cost. In this paper we present an efficient, non-intrusive FPGA-based application profiler to address this aspect. Unlike other profilers, our proposed approach does not involve any modification at the hardware level in the actual implementation of any chosen processor and neither is there any need to re-synthesize the profiler to profile any new application.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116883083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Tag only storage for capacity optimised last level cache in chip multiprocessors 标签仅存储容量优化的最后一级缓存在芯片多处理器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064886

Surajit Das, Shirshendu Das, H. Kapoor

{"title":"Tag only storage for capacity optimised last level cache in chip multiprocessors","authors":"Surajit Das, Shirshendu Das, H. Kapoor","doi":"10.1109/ISVDAT.2016.8064886","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064886","url":null,"abstract":"Last Level Cache (LLC) plays an important role in increasing overall system performance of chip multiprocessor (CMP). The cores in a CMP has a private cache and a shared LLC whose size increases with each process generation. It has been observed that for different application on average 24% of the blocks are privately owned by the cores, and that the copies of these blocks in the LLC are redundant. This suggests that one needs to maintain only the tag portion of such private blocks in the LLC. Existing research has attempted to do this by partitioning the cache into tag-only and tag+data storage sections. This reduces the overall area of the LLC, but can degrade the performance to some extent. The tag-only storage stores the tags of the private blocks and if there are more such blocks in a set then these occupy the ways from the tag+data part. Thus, the chances of tag+data blocks staying in the cache reduces, affecting the performance. In this paper we propose to rectify the performance degradation by allowing more storage for the tag-only as well as tag+data parts. This is done by dynamically increasing the associativity of the sets. Experimental evaluation shows significant performance improvement with comparable area savings.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129029063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives 基于提高精度的能量检测的认知无线电无线传感器:性能和硬件角度

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064871

R. Shrestha, Vinay Swargam, M. S. Murty

{"title":"Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives","authors":"R. Shrestha, Vinay Swargam, M. S. Murty","doi":"10.1109/ISVDAT.2016.8064871","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064871","url":null,"abstract":"This paper presents new system-level design for the cognitive sensor based on energy detection to boast the performance accuracy by maintaining a queue of energy samples and computing their average to determine the decision threshold. Thereafter, these values summed over average number of samples are again compared with the recent energy value to decide whether the spectrum is occupied or unoccupied more accurately. The performance of such technique is evaluated analytically for various decision thresholds. Such evaluations indicate that the some advancements made to the energy detection algorithm has demonstrated improvements in the spectrum sensing accuracy under varying signal to noise ratio (SNR) values. Subsequently, we have shown the benefits of the proposed scheme in increasing the agility of cognitive radio systems. The performance is measured by using the receiver operating characteristic (ROC) curves under varying number of levels for different SNR values like: −5 dB, −10 dB, −15 dB and −20 dB. With small tradeoffs between the detection probability and the false alarm probability, the scheme improves the spectrum sensing ability greatly in low SNR situations when tested with 10, 100, 1000, 10000 and 100000 samples. Thereby, enhancing the performance of such hardware friendly sensors under low SNR has been a potential achievement of our work. Finally, field-programmable gate-array (FPGA) prototyping of the proposed sensor architecture has been carried out and it has a latency of 21760 nS.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131463421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Smart handheld platform for electrochemical bio sensors 智能手持电化学生物传感器平台

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064906

Suraj Hebbar, Vinay Kumar, M. S. Bhat, N. Bhat

引用次数: 0

FFT/IFFT implementation using Vivado™ HLS 使用Vivado™HLS实现FFT/IFFT

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064896

Amit Salaskar, N. Chandrachoodan

引用次数: 5