基于ΣΔ调制技术的闭环MEMS电容式加速度计设计方法

P. Chatterjee, S. Kar, S. Sen
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引用次数: 1

摘要

本文介绍了一种基于σ - δ调制技术的闭环微机电系统(MEMS)电容式加速度计系统的设计过程。在Cadence模拟设计环境下,采用UMC 180nm工艺设计了一种信号调理集成电路。为了对整个系统进行详细的仿真,MEMS器件也被同一平台上的等效电模型所取代。由于闭环系统可能存在稳定性问题,本文还讨论了适当系数的引线补偿器设计。该程序可用于设计和分析不同类型的闭环MEMS电容加速度计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design methodology of closed loop MEMS capacitive accelerometers based on ΣΔ modulation technique
This paper presents the design procedure for thorough analysis of a closed loop Micro-Electro-Mechanical Systems (MEMS) capacitive accelerometer system based on sigma-delta modulation technique. A signal conditioning IC has been designed in UMC 180 nm process in Cadence Analog Design Environment. To perform detailed simulation of the entire system, the MEMS device has also been replaced by its electrical equivalent model on the same platform. Since the closed loop system may suffer from stability issue, a lead compensator design with proper coefficients has also been discussed. The procedure can be followed for the design and analysis of different types of closed loop MEMS capacitive accelerometers.
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