2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献_第5页

Data dependent spurious power reduction for fixed width multiplier 固定宽度乘法器的数据相关杂散功率降低

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064898

Bharti Navlani, P. Joshi, R. Deshmukh

引用次数: 0

Approximate conditional carry adder for error tolerant applications 用于容错应用的近似条件进位加法器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064867

Avishek Sinha Roy, N. Prasad, A. Dhar

引用次数: 2

Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401–406 MHz frequency band 用于401-406 MHz频段的MedRadio接收机链中的低噪声放大器的设计和测量技术

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064846

Abhishek Srivastava, Nithin Sankar, K. K. Rakesh, Baibhab Chatterjee, D. Das, M. Baghini

引用次数: 1

An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique 一种采用中国算盘技术的8位500 MSPS分段电流转向DAC

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064903

S. Khandagale, Santanu Sarkar

{"title":"An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique","authors":"S. Khandagale, Santanu Sarkar","doi":"10.1109/ISVDAT.2016.8064903","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064903","url":null,"abstract":"This paper proposes the design of an 8-bit segmented current steering (CS) digital to analog converter (DAC), which uses Chinese abacus technique to improve both static and dynamic performances. Chinese abacus DAC is simple, occupies less area and shows better linearity compared to binary DAC. In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary. In this design the binary section of segmented architecture is replaced by Chinese abacus sub-DAC to minimize noise i.e., glitch energy and to improve the spurious performance. The modified CS architecture is segmented as 4+4 to achieve optimum performance and to minimise area. The four most significant bits (MSBs) and four least significant bits (LSBs) are implemented in unary and Chinese abacus sub-DAC, respectively. The proposed 8-bit segmented CS-DAC schematic has been designed and simulated in UMC 0.18 μm CMOS process technology. The proposed CS-DAC shows better SFDR over conventional DAC. The DAC consumes only 4.63 mW of power at 103.5 MHz input signal. The proposed design could be used as ready-made IP in GSM transmitter.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128686706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC 预先布局模块明智的decap分配，以抑制SoC的噪声和准确的延迟估计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064873

Moumita Chakraborty, A. Chakrabarti, P. Mitra, Debasri Saha, Krishnendu Guha

{"title":"Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC","authors":"Moumita Chakraborty, A. Chakrabarti, P. Mitra, Debasri Saha, Krishnendu Guha","doi":"10.1109/ISVDAT.2016.8064873","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064873","url":null,"abstract":"This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement of decoupling capacitors for system on chip (SoC) design. But, early prediction and allocation of decaps at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing power, noise and delay effects for the circuit. The novelty of our work lies in exhaustive module wise estimation of di/dt drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay and noise performance to its best. We choose Double DES as example crypto-core for our test circuits as this is quite complex in nature and are also used as custom cores in many SoC applications. We investigate the change in power, noise and delay parameters with and without the decap allocation for multi-core circuits at the pre-layout stage and find satisfactory suppression of noise at the cost of negligible increase in power and delay. By using our approach, average peak noise and maximum peak noise can be suppressed approximately by 22.7% and 32.23% respectively at the pre-layout stage comparing with the previous works. This early prediction helps in more accurate Computer Aided Design (CAD) implementation at the layout stage.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125231166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reducing FIFO buffer power using architectural alternatives at RTL 在RTL中使用架构替代方案降低FIFO缓冲区功率

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064897

Ashish Sharma, Ruby Ansar, M. Gaur, Lava Bhargava, V. Laxmi

引用次数: 2

Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell 7T和8T SRAM电池在阈下区域的性能量化及其与常规6T SRAM电池的比较

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064899

Pulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, S. Darak

引用次数: 4

Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects 基于侧接触多层石墨烯纳米带的电源互连中温度相关的红外降和延迟分析

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064891

S. Bhattacharya, Debaprasad Das, H. Rahaman

引用次数: 1

Golden IC free methodology for hardware Trojan detection using symmetric path delays 使用对称路径延迟的硬件木马检测的黄金IC自由方法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064895

Ramakrishna Vaikuntapu, Lava Bhargava, V. Sahula

引用次数: 5

A novel low power 6-bit FLASH ADC using charge steering amplifier for RF applications 一种新颖的低功耗6位FLASH ADC，采用电荷转向放大器用于射频应用

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064904

K. K. Movva, Syed Azeemuddin

引用次数: 3