An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique

This paper proposes the design of an 8-bit segmented current steering (CS) digital to analog converter (DAC), which uses Chinese abacus technique to improve both static and dynamic performances. Chinese abacus DAC is simple, occupies less area and shows better linearity compared to binary DAC. In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary. In this design the binary section of segmented architecture is replaced by Chinese abacus sub-DAC to minimize noise i.e., glitch energy and to improve the spurious performance. The modified CS architecture is segmented as 4+4 to achieve optimum performance and to minimise area. The four most significant bits (MSBs) and four least significant bits (LSBs) are implemented in unary and Chinese abacus sub-DAC, respectively. The proposed 8-bit segmented CS-DAC schematic has been designed and simulated in UMC 0.18 μm CMOS process technology. The proposed CS-DAC shows better SFDR over conventional DAC. The DAC consumes only 4.63 mW of power at 103.5 MHz input signal. The proposed design could be used as ready-made IP in GSM transmitter.