2016 20th International Symposium on VLSI Design and Test (VDAT)最新文献_第4页

Hardware optimizations for crypto implementations (Invited paper) 加密实现的硬件优化(特邀论文)

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064877

M. Basiri, Sandeep K. Shukla

引用次数: 4

Formal verification of switched capacitor DC to DC power converter using circuit simulation traces 正式验证的开关电容DC到DC功率转换器使用电路仿真走线

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064894

A. Mishra, S. Roy

引用次数: 0

Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff 双版式光刻(DPL)-兼容布局结构(DCLC)与面积线使用权衡

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064875

D. Pal, Abir Pramanik, P. Dasgupta, D. K. Das

{"title":"Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff","authors":"D. Pal, Abir Pramanik, P. Dasgupta, D. K. Das","doi":"10.1109/ISVDAT.2016.8064875","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064875","url":null,"abstract":"A layout decomposition in Double Patterning Lithography (DPL) is considered to be potential for processing nodes at or below 32 nm. In this method, two features are assigned different colors corresponding to different exposures if the spacing between them is less than a minimum value defined by design-specific rules. In general, there are cases where such different colors assignment may not be possible even though the inter-feature spacing is less than the specified minimum. This condition is often known as color conflict of adjacent features. Color conflicts are traditionally resolved by splitting the features. This problem is often modeled as a graph-theoretic problem, with color conflicts identified as odd-cycle detection, and the duplication of vertices of the graph arising out of splitting of features of a layout. However, for a given layout, the splitting of features may not always be desirable or even feasible. In this paper, we propose a merge-only technique with conservative application of de-compaction so that the overall area of the layout is minimally affected. We consider layouts having rectilinear features present in the layout and apply the proposed algorithm to obtain a DPL-compliant layout with selective use of stitches keeping the overall layout area fixed. Experimental results with some standard layouts demonstrate the effectiveness of the proposed algorithm.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128732128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low-power high-speed hybrid full adder 一种低功耗高速混合全加法器

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064900

Manan Mewada, M. Zaveri

引用次数: 6

Planning based guided reconstruction of corner cases in architectural validation 在架构验证中，基于指导重构的边缘案例的规划

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064887

R. L. Jana, Shashank Kuchibhotla, Soumyajit Dey, P. Dasgupta, Rakesh Kumar

引用次数: 2

Skip-scan: A methodology for test time reduction 跳过扫描:一种减少测试时间的方法

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064869

Binod Kumar, B. Nehru, B. Pandey, Jaynarayan T. Tudu

引用次数: 1

Design of fault tolerant majority voter for TMR circuit in QCA QCA中TMR电路容错多数投票人设计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064905

Subrata Chattopadhyay, Shiv Bhushan Tripathi, Mrinal Goswami, B. Sen

引用次数: 4

Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations 参数变化下不同容量SRAM子系统的建模与成品率估计

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064840

Pulkit Sharma, Anil Kumar Gundu, M. Hashmi

{"title":"Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations","authors":"Pulkit Sharma, Anil Kumar Gundu, M. Hashmi","doi":"10.1109/ISVDAT.2016.8064840","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064840","url":null,"abstract":"Process variations have become a major challenge with the advancement in CMOS technologies. The performance of memory sub-systems such as Static Random Access Memory (SRAMs) is heavily dependent on these variations. Also, the VLSI industry requires the SRAM bit cell to qualify in the order of less than 0.1ppb to achieve higher Yield (Y). This paper proposes an efficient qualitative statistical analysis and Yield estimation method of SRAM sub-system which considers deviations due to variations in process parameters in bit line differential and input offset of sense amplifier (SA) all together. The Yield of SRAM is predicted for different capacities of SRAM array by developing a statistical model of memory sub-system in 65nm bulk CMOS technology. For the sub-system with 64 bit cells, it is estimated that the probability of failure is 4.802 ∗ 10−13 in a read cycle of frequency 1GHz. Furthermore, the probability of failure for 8MB capacity is 5.035 ∗ 10−7 while for 2GB capacity it increases to 1.289 ∗ 10−5. It is also observed that as the load on one SA per column is doubled, the probability of failure of memory slice increases by 70%. The proposed technique estimates the Yield(Y) for SRAM array to be more than 99.9999.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers 多标准无线通信接收机高速可重构滤波器组的FPGA实现

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064855

Sasha Garg, S. Darak

{"title":"FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers","authors":"Sasha Garg, S. Darak","doi":"10.1109/ISVDAT.2016.8064855","DOIUrl":"https://doi.org/10.1109/ISVDAT.2016.8064855","url":null,"abstract":"In next generation wireless communication system, wireless transceivers should be able to handle wideband input signals compromising of multiple communication standards. Such multi-standard wireless communication receivers (MWCRs) need filter bank to extract the desired signal of interest from wideband input spectrum and bring it to the baseband for further signal processing tasks such as spectrum sensing, modulation classification, demodulation etc. In MWCRs, rather any wireless receivers, modulated filter banks, such as Discrete Fourier Transform Filter Banks (DFTFB), are preferred due to their advantages such as lower area, delay and power requirements. To support multi-standard operation, reconfigurable DFTFB (RDFTFB) was proposed by integrating DFTFB with the coefficient decimation method. In this paper, an efficient high speed implementation of RDFTFB on Virtex-7 field programmable gate arrays (FPGA) has been proposed. The proposed approach minimizes the critical path delay between clocked registers thereby leading to significant improvement in the maximum operating frequency of the RDFTFB. Numerically, the proposed implementation leads to 89.7% improvement in the maximum frequency at which RDFTFB can be clocked. Furthermore, proposed implementation leads to 18.5% reduction in the dynamic power consumption.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128212390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata t门:量子点元胞自动机中部分极化的概念

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI: 10.1109/ISVDAT.2016.8064844

Chiradeep Mukherjee, S. Roy, Saradindu Panda, B. Maji

引用次数: 13