Planning based guided reconstruction of corner cases in architectural validation

Validation of modern microprocessors is a time consuming as well as complex process where constraint-based random test inputs are used to sensitize and monitor whether the hardware execution logic exhibits the desired micro-architectural event sequences. Such testing methods often lead to bug scenarios revealed as simulation traces which serve as the basis for patching the RTL code in order to fix a possible bug. However, the bug fix can be local in nature in the sense that the bug may possibly manifest itself in an alternate execution trace. The present work leverages AI planning to develop techniques for automatic construction of test programs for sensitizing deep architectural bugs by reproducing a bug scenario as different possible sequences of micro-architectural events given that the scenario was initially observed as one such sequence in a simulation trace. Automated generation of such test programs 1) help to evaluate the robustness of a given bug fix or alternatively 2) identify the root cause of the bug so that a proper fix can be carefully planned.