Skip-scan: A methodology for test time reduction

Abstract

Reducing test time is a major challenge in scan based DFT architectures for cost effective test. In this paper, we have proposed a test pattern reordering methodology for dynamic scan architecture. The reconfiguration of scan chain dynamically reduces its length by skipping scan cells with don't care bits. A graph theoretical approach is presented for test pattern reordering to maximise skip. We have calculated theoretical bounds on reduction in test time and segregated test patterns into groups with variable skip-depths. Our results indicate up to 84% reduction in test time. Comparison of this approach with the default ATPG tool pattern and scan chain reordering technique is also done.