Planning based guided reconstruction of corner cases in architectural validation

2016 20th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2016-05-01 DOI:10.1109/ISVDAT.2016.8064887

R. L. Jana, Shashank Kuchibhotla, Soumyajit Dey, P. Dasgupta, Rakesh Kumar

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引用次数: 2

Abstract

Validation of modern microprocessors is a time consuming as well as complex process where constraint-based random test inputs are used to sensitize and monitor whether the hardware execution logic exhibits the desired micro-architectural event sequences. Such testing methods often lead to bug scenarios revealed as simulation traces which serve as the basis for patching the RTL code in order to fix a possible bug. However, the bug fix can be local in nature in the sense that the bug may possibly manifest itself in an alternate execution trace. The present work leverages AI planning to develop techniques for automatic construction of test programs for sensitizing deep architectural bugs by reproducing a bug scenario as different possible sequences of micro-architectural events given that the scenario was initially observed as one such sequence in a simulation trace. Automated generation of such test programs 1) help to evaluate the robustness of a given bug fix or alternatively 2) identify the root cause of the bug so that a proper fix can be carefully planned.

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在架构验证中，基于指导重构的边缘案例的规划

现代微处理器的验证是一个耗时且复杂的过程，其中使用基于约束的随机测试输入来敏感和监控硬件执行逻辑是否显示所需的微体系结构事件序列。这样的测试方法通常会导致以模拟跟踪的形式显示的错误场景，这些跟踪可以作为修补RTL代码以修复可能的错误的基础。然而，bug修复本质上可能是局部的，因为bug可能在另一个执行跟踪中出现。目前的工作利用人工智能计划来开发测试程序的自动构建技术，通过将错误场景作为不同可能的微架构事件序列重现，从而对深层架构错误敏感，因为该场景最初是作为模拟跟踪中的一个这样的序列观察到的。此类测试程序的自动生成1)有助于评估给定错误修复的健壮性，或者2)识别错误的根本原因，以便可以仔细计划适当的修复。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 20th International Symposium on VLSI Design and Test (VDAT)

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