Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC

Abstract

This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement of decoupling capacitors for system on chip (SoC) design. But, early prediction and allocation of decaps at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing power, noise and delay effects for the circuit. The novelty of our work lies in exhaustive module wise estimation of di/dt drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay and noise performance to its best. We choose Double DES as example crypto-core for our test circuits as this is quite complex in nature and are also used as custom cores in many SoC applications. We investigate the change in power, noise and delay parameters with and without the decap allocation for multi-core circuits at the pre-layout stage and find satisfactory suppression of noise at the cost of negligible increase in power and delay. By using our approach, average peak noise and maximum peak noise can be suppressed approximately by 22.7% and 32.23% respectively at the pre-layout stage comparing with the previous works. This early prediction helps in more accurate Computer Aided Design (CAD) implementation at the layout stage.