Data dependent spurious power reduction for fixed width multiplier

Abstract

Digital Signal Processing (DSP) algorithms use multiplication as a most frequent operation. Hence multipliers are said to be dominant role players in the performance matrix of DSP application. The Fixed Width Multiplier (FWM) architecture in DSP application, itself are power efficient, most of the related work is reported on error correction. This paper extends the work of one of the bests papers reported on error correction for power reduction of biomedical signal processing applications. We achieve this by reducing the dynamic power in the retained elements in the FWM using bypassing techniques. The decision of augmenting a bypassing and error correcting circuit of a FWM is taken based on the column wise probability analysis carried out on partial product array of FWM. We observed this probability lies in between 0.1 to 0.4. Hence this best reported error optimized architecture is applied with bypassing technique. We observe the 13.9% of improved power performance using this technique.