An efficient FPGA-based function profiler for embedded system applications

Abstract

Modern embedded systems are typically implemented using both programmable processors and application specific hardware in order to meet real time design goals, besides other metrics, such as, performance, area and cost. The availability of programmable processors and application specific hardware enables an application architect to partition the execution of the given application code (specified in some high-level language) optimally; so as to execute as large a portion of it, which is timing or performance non-critical, on the processor to lower implementation cost and the timing critical rest, in expensive application specific digital hardware, implemented either as an ASIC or programmed into a FPGA. Profiling tools enables this optimal partitioning by monitoring the execution of the application code running on a processor and capturing different characteristics of the program execution. One of the important aspect that needs to be profiled is the cost of executing functions or subroutines, in terms of both the computational cost, as well as, the communication cost. In this paper we present an efficient, non-intrusive FPGA-based application profiler to address this aspect. Unlike other profilers, our proposed approach does not involve any modification at the hardware level in the actual implementation of any chosen processor and neither is there any need to re-synthesize the profiler to profile any new application.