{"title":"Switched-capacitor circuit simulator in Q-V domain including nonidealities","authors":"G. Muralidhar, Dinesh Ganesan, B. Kailath","doi":"10.1109/ISVDAT.2016.8064865","DOIUrl":null,"url":null,"abstract":"Circuit simulations need to be performed as a pre-manufacturing design strategy for checking and verifying design of electrical and electronic circuits and systems. Switched capacitor circuits belong to a class of circuits where signal processing is performed by charge redistribution among series of capacitors based on the configuration. In order to simulate the true characteristics of such circuits, the simulator should be capable of, formulating the circuit parameters based on charge redistribution rather than current-voltage relationship and, including non-idealities such as charge injection, parasitic capacitance effect, improper charge redistribution causing settling error etc. A switched capacitor circuit simulator addressing charge redistribution is presented in this paper. It works on the principle of quantifying all circuit parameters based on charge-voltage formulation which enables linearized approximation for nonlinear characteristics while evaluating the time response. The proposed simulator also incorporates nonideality of charge leakage and nonlinear capacitance. It permits piecewise constant and continuous inputs for evaluating the time response and employs numerical techniques such as Gauss elimination and LU factorization to solve equations. The linearized formulation enables shorter simulation time which otherwise requires many clock cycles and provides better convergence and accuracy. Three sample circuits are considered to validate the performance of the simulator. The entire simulator is developed in PYTHON environment taking SPICE type netlist as inputs.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 20th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2016.8064865","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Circuit simulations need to be performed as a pre-manufacturing design strategy for checking and verifying design of electrical and electronic circuits and systems. Switched capacitor circuits belong to a class of circuits where signal processing is performed by charge redistribution among series of capacitors based on the configuration. In order to simulate the true characteristics of such circuits, the simulator should be capable of, formulating the circuit parameters based on charge redistribution rather than current-voltage relationship and, including non-idealities such as charge injection, parasitic capacitance effect, improper charge redistribution causing settling error etc. A switched capacitor circuit simulator addressing charge redistribution is presented in this paper. It works on the principle of quantifying all circuit parameters based on charge-voltage formulation which enables linearized approximation for nonlinear characteristics while evaluating the time response. The proposed simulator also incorporates nonideality of charge leakage and nonlinear capacitance. It permits piecewise constant and continuous inputs for evaluating the time response and employs numerical techniques such as Gauss elimination and LU factorization to solve equations. The linearized formulation enables shorter simulation time which otherwise requires many clock cycles and provides better convergence and accuracy. Three sample circuits are considered to validate the performance of the simulator. The entire simulator is developed in PYTHON environment taking SPICE type netlist as inputs.