FFT/IFFT implementation using Vivado™ HLS

Abstract

High level synthesis tools are an attractive option for rapid prototyping and implementation of hardware designs. In this paper we present a case study of using such a tool for the design and implementation of an FFT core for use in a wireless modem. The optimizations used for directing the conversion of C code to hardware are discussed and the impact of the different directives is analyzed. The resulting hardware architecture is competitive with the highly optimized IP core available from Xilinx for their FPGAs in terms of the hardware requirements while achieving a slightly better latency for the same configuration.