Tag only storage for capacity optimised last level cache in chip multiprocessors

Abstract

Last Level Cache (LLC) plays an important role in increasing overall system performance of chip multiprocessor (CMP). The cores in a CMP has a private cache and a shared LLC whose size increases with each process generation. It has been observed that for different application on average 24% of the blocks are privately owned by the cores, and that the copies of these blocks in the LLC are redundant. This suggests that one needs to maintain only the tag portion of such private blocks in the LLC. Existing research has attempted to do this by partitioning the cache into tag-only and tag+data storage sections. This reduces the overall area of the LLC, but can degrade the performance to some extent. The tag-only storage stores the tags of the private blocks and if there are more such blocks in a set then these occupy the ways from the tag+data part. Thus, the chances of tag+data blocks staying in the cache reduces, affecting the performance. In this paper we propose to rectify the performance degradation by allowing more storage for the tag-only as well as tag+data parts. This is done by dynamically increasing the associativity of the sets. Experimental evaluation shows significant performance improvement with comparable area savings.