A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness

Abstract

Chip Multiprocessor (CMP) and System-on-Chip (SoC) designs have a large number of modules with billions of transistors embedded on a single die. While they offer very high performance, they also increase the design complexity and pose many challenges with one of them being floor-planning and placement. Floor-planning process is affected by and in turn effects physical characteristics, wire length, propagation delay between modules, power and thermal density of the chip. Floor-planning at backend generally takes considerable amount of runtime. With large design space of CMP/SoC designs, it is not possible to explore multiple options or rerun the process in case of discrepancies. In this work, we propose and develop a pre-RTL tool framework that performs floor-planning analysis at early stages of development. The primary goal is to perform floor-plan analysis using abstract description of a design. The tool explores multiple layout options for a design and provide insights into different physical aspects like area, relative position of IPs, thermal and power performance. Since detailed physical information is not required at early stages, it allows us to explore the vast design space of SoCs. The tool is written in python and is based on simulated annealing algorithm which is adapted to the problem's context. We demonstrate the utility and robustness of the tool in providing multiple layout options with different user specifications.