Design of coherence verification unit for CMPs realizing dragon protocol

Abstract

The data coherence in Chip Multiprocessors (CMPs) cache system is to be more accurate and reliable. A system with single producer and multiple consumers uses update based coherence protocol (dragon). This work proposes an effective solution for coherence verification in dragon through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length cycle single attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of dragon. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.