{"title":"一种用于非易失性存储器的高速低压锁存器型感测放大器","authors":"Disha Arora, Anil Kumar Gundu, M. Hashmi","doi":"10.1109/ISVDAT.2016.8064841","DOIUrl":null,"url":null,"abstract":"A high speed low power modified latch type static sense amplifier design for current sensing in non-volatile memories is presented in this paper. The idea presented in this paper makes use of the fact that the scaling in technology introduces severe reliability issues in sensing circuits, due to device mismatches, which cause unpredictability in their performance metrics. In this paper, a detailed analysis on the proposed sense amplifier topology has been carried out by introducing variations in the threshold voltage of the devices to determine its impact on the performance metrics such as sensing delay, offset, and power. The proposed sense amplifier exhibits a worst case sensing delay of 0.946ns and allows operation at power supplies lower than 1.2V. This design is capable of working at a current offset of 1μΑ, consumes total power of 45.512μW at 27°C with an improvement of 32.6% in power consumption when compared to conventional designs.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A high speed low voltage latch type sense amplifier for non-volatile memory\",\"authors\":\"Disha Arora, Anil Kumar Gundu, M. Hashmi\",\"doi\":\"10.1109/ISVDAT.2016.8064841\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high speed low power modified latch type static sense amplifier design for current sensing in non-volatile memories is presented in this paper. The idea presented in this paper makes use of the fact that the scaling in technology introduces severe reliability issues in sensing circuits, due to device mismatches, which cause unpredictability in their performance metrics. In this paper, a detailed analysis on the proposed sense amplifier topology has been carried out by introducing variations in the threshold voltage of the devices to determine its impact on the performance metrics such as sensing delay, offset, and power. The proposed sense amplifier exhibits a worst case sensing delay of 0.946ns and allows operation at power supplies lower than 1.2V. This design is capable of working at a current offset of 1μΑ, consumes total power of 45.512μW at 27°C with an improvement of 32.6% in power consumption when compared to conventional designs.\",\"PeriodicalId\":301815,\"journal\":{\"name\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 20th International Symposium on VLSI Design and Test (VDAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVDAT.2016.8064841\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 20th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2016.8064841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high speed low voltage latch type sense amplifier for non-volatile memory
A high speed low power modified latch type static sense amplifier design for current sensing in non-volatile memories is presented in this paper. The idea presented in this paper makes use of the fact that the scaling in technology introduces severe reliability issues in sensing circuits, due to device mismatches, which cause unpredictability in their performance metrics. In this paper, a detailed analysis on the proposed sense amplifier topology has been carried out by introducing variations in the threshold voltage of the devices to determine its impact on the performance metrics such as sensing delay, offset, and power. The proposed sense amplifier exhibits a worst case sensing delay of 0.946ns and allows operation at power supplies lower than 1.2V. This design is capable of working at a current offset of 1μΑ, consumes total power of 45.512μW at 27°C with an improvement of 32.6% in power consumption when compared to conventional designs.