Frequency domain analysis of on-chip power distribution network

Abstract

The noise induced by variations in power supply adversely effects System-on-chip (SoC) performance and these effects could be understood through modelling and analysis of Power Distribution Network (PDN). This paper presents modelling of PDN by incorporation of BGR and LDO for analyzing the effect of supply induced noise on the PDN performance. The effect of Simultaneous Switching Noise (SSN) resulting from switching of various analog and digital sub-systems is assessed through power spectral density curves. Finally, an appropriate PDN topology is proposed for connecting the sub-systems on a chip by considering the minimal effect of simultaneous switching noise on output as the main criterion.