A high speed low voltage latch type sense amplifier for non-volatile memory

Disha Arora, Anil Kumar Gundu, M. Hashmi
{"title":"A high speed low voltage latch type sense amplifier for non-volatile memory","authors":"Disha Arora, Anil Kumar Gundu, M. Hashmi","doi":"10.1109/ISVDAT.2016.8064841","DOIUrl":null,"url":null,"abstract":"A high speed low power modified latch type static sense amplifier design for current sensing in non-volatile memories is presented in this paper. The idea presented in this paper makes use of the fact that the scaling in technology introduces severe reliability issues in sensing circuits, due to device mismatches, which cause unpredictability in their performance metrics. In this paper, a detailed analysis on the proposed sense amplifier topology has been carried out by introducing variations in the threshold voltage of the devices to determine its impact on the performance metrics such as sensing delay, offset, and power. The proposed sense amplifier exhibits a worst case sensing delay of 0.946ns and allows operation at power supplies lower than 1.2V. This design is capable of working at a current offset of 1μΑ, consumes total power of 45.512μW at 27°C with an improvement of 32.6% in power consumption when compared to conventional designs.","PeriodicalId":301815,"journal":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 20th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVDAT.2016.8064841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

A high speed low power modified latch type static sense amplifier design for current sensing in non-volatile memories is presented in this paper. The idea presented in this paper makes use of the fact that the scaling in technology introduces severe reliability issues in sensing circuits, due to device mismatches, which cause unpredictability in their performance metrics. In this paper, a detailed analysis on the proposed sense amplifier topology has been carried out by introducing variations in the threshold voltage of the devices to determine its impact on the performance metrics such as sensing delay, offset, and power. The proposed sense amplifier exhibits a worst case sensing delay of 0.946ns and allows operation at power supplies lower than 1.2V. This design is capable of working at a current offset of 1μΑ, consumes total power of 45.512μW at 27°C with an improvement of 32.6% in power consumption when compared to conventional designs.
一种用于非易失性存储器的高速低压锁存器型感测放大器
提出了一种用于非易失性存储器电流检测的高速低功耗改进锁存式静态感测放大器设计。本文提出的想法利用了这样一个事实,即技术中的缩放在传感电路中引入了严重的可靠性问题,这是由于设备不匹配导致其性能指标的不可预测性。在本文中,通过引入器件阈值电压的变化来确定其对性能指标(如传感延迟、偏移和功率)的影响,对所提出的感测放大器拓扑结构进行了详细分析。所提出的感测放大器表现出0.946ns的最坏情况感测延迟,并允许在低于1.2V的电源下工作。该设计能够在1μΑ电流偏置下工作,27°C时的总功耗为45.512μW,与传统设计相比功耗提高了32.6%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信