An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI

Abstract

In advanced technology nodes, device variations limit the SRAM performance and yield. Cell stability defined by the Static Noise Margin (SNM) of the SRAM cell primarily governs the performance with respect to yield in SRAMs. Variations in the scaled SRAMs increase the probability of cells becoming weak. To ensure reliability of SRAMs it is important to identify such cells post silicon. In this work, we propose a correlation based test methodology to detect the weak bits in SRAMs with respect to SNM. We present a case study for 64×64 SRAM in 28nm FDSOI technology. The proposed methodology targets high speed testing and lower test costs. It enables to perform the test at nominal operating voltage and room temperature. Suitable read stress is induced by boosting the Word Line (WL) voltage of the 6T SRAM cell. To validate the effectiveness of the test and find appropriate test stress we propose correlation methodology. With this test we could detect the weak cells possessing SNM upto 60mV across various process corners for stress voltage ranging from 1.14V to 1.16V. Moreover, it requires minimal area penalty and test time compared to standard tests.