JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power

Abstract

Traditionally, serial scan architecture have been predominantly used as a DFT technique for most of the designs. However, shrinking technology and increasing design complexity has brought a set of new test challenges. It initiates new research direction to explore innovative DFT architecture. This paper proposes a new DFT architecture, named as Joint-scan. The proposed architecture provides a solution for the test time, test data volume, and test power problems simultaneously. The primary idea here is to bring in the key advantages of serial scan and random access scan in a single architecture. The effectiveness of the proposed architecture has been demonstrated through experimental results by comparing with the state-of-the-art random access scan, and multiple sequential scan architecture. The results show promising reduction in test time, data volume, and test power.