Energy-efficient reconfigurable framework for evaluating hybrid NoCs

Abstract

The advancements in emerging interconnects for Networks-on-Chip (NoCs) brings with it promising solutions to integrate single-hop long-range high-bandwidth on-chip links to achieve enhanced network performance. The use of these lie in the design of modern heterogeneous systems with increasing number of processing blocks, which may include application specific unconventional topologies. In this work, we present a reconfigurable simulation framework that enables evaluation of such complex designs and in the process, introduce a new cost-effective metric based on network utilization and illustrate how it can be exploited to achieve energy efficient NoCs by implementing low power design strategies like Dynamic Voltage Scaling (DVS) and power-gating. An experimental setup and evaluation follows for both regular and hybrid topologies under synthetic and application specific traffic. This work will enable quick and detailed evaluation of hybrid topologies. The results achieved clearly establish the cost-effectiveness of the proposed framework.