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2009 IEEE International Interconnect Technology Conference最新文献

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A Wafer-Level 3D Integration Using Bottom-Up Copper Electroplating and Hybrid Metal-Adhesive Bonding 基于自底向上镀铜和混合金属粘接的晶圆级三维集成
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090374
Chongshen Song, Zheyao Wang, Zhimin Tan, Litian Liu
{"title":"A Wafer-Level 3D Integration Using Bottom-Up Copper Electroplating and Hybrid Metal-Adhesive Bonding","authors":"Chongshen Song, Zheyao Wang, Zhimin Tan, Litian Liu","doi":"10.1109/IITC.2009.5090374","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090374","url":null,"abstract":"We report a wafer-level 3D integration scheme using bottom-up copper electroplating (BCE) and hybrid metal-adhesive wafer bonding. Through-silicon-vias (TSVs) with aspect ratio as high as 13 are plated using BCE without forming voids/seams. Cu-Sn bumps electroplated on the TSVs are used together with polymer adhesive for hybrid bonding. A two-layer 3D integration is achieved using BCE and hybrid bonding, validating the feasibility in fabricating wafer-level 3D integration with high aspect ratio TSVs.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132036679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cobalt and nickel atomic layer depositions for contact applications 接触应用的钴和镍原子层沉积
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090371
Han‐Bo‐Ram Lee, W. Kim, Yongjun Park, S. Baik, Hyungjun Kim
{"title":"Cobalt and nickel atomic layer depositions for contact applications","authors":"Han‐Bo‐Ram Lee, W. Kim, Yongjun Park, S. Baik, Hyungjun Kim","doi":"10.1109/IITC.2009.5090371","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090371","url":null,"abstract":"Novel NH3-based Co thermal atomic layer deposition (T-ALD) process using Co(iPr-AMD)2 (bis(N,N'-diisopropylacetamidinato) cobalt(II)) and NH3 as a precursor and a reactant, respectively, was developed for nanoscale contact applications. The T-ALD Co films showed high purity with perfect conformality inside nanosize contact holes. By annealing the T-ALD Co films, CoSi2 was obtained. Similarly, Ni T-ALD process using NH3 as a reactant was also investigated by using Ni(dmamb)2 (bis(dimethylamino-2-methyl-2-butoxo)nickel) and Ni films showed perfect conformality of T-ALD Ni.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128983123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Back-end-of-line integration approaches for resistive memories 电阻式存储器的后端集成方法
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090335
V. Jousseaume, J. Buckley, Y. Bernard, P. Gonon, C. Vallée, M. Mougenot, H. Feldis, S. Minoret, G. Chamiot-Maitral, A. Persico, A. Zenasni, M. Gely, J. Barnes, E. Martinez, H. Grampeix, C. Guedj, J. Nodin, B. De Salvo
{"title":"Back-end-of-line integration approaches for resistive memories","authors":"V. Jousseaume, J. Buckley, Y. Bernard, P. Gonon, C. Vallée, M. Mougenot, H. Feldis, S. Minoret, G. Chamiot-Maitral, A. Persico, A. Zenasni, M. Gely, J. Barnes, E. Martinez, H. Grampeix, C. Guedj, J. Nodin, B. De Salvo","doi":"10.1109/IITC.2009.5090335","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090335","url":null,"abstract":"This work deals with the development of resistive memories based on oxides and their integration into the interconnection levels. The paper is focused on the screening of different dielectric oxides (metallic or not) showing resistive switching properties in order to lead to the highest performance resistive memories. Nickel oxide which is the most studied material in the literature is compared to other binary metallic oxides. In parallel, cells with silicon based dielectrics and Cu electrodes were developed. Electrical results allowed a comparison between the 3 main mechanisms observed in resistive memories based on oxides. Moreover, a specific resist flowing process and ion beam etching were optimized in order to limit metallic residues on memory cell side walls and prevent short-circuiting.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116406951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
In situ post etching treatment as a solution to improve defect density for porous low-k integration using metallic hard masks 原位后蚀刻处理作为一种解决方案，以提高使用金属硬掩模多孔低钾集成的缺陷密度
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090398
N. Possémé, R. Bouyssou, T. Chevolleau, T. David, V. Arnal, S. Chhun, C. Monget, E. Richard, D. Galpin, J. Guillan, L. Arnaud, D. Roy, M. Guillermet, J. Ramard, O. Joubert, C. Verove
{"title":"In situ post etching treatment as a solution to improve defect density for porous low-k integration using metallic hard masks","authors":"N. Possémé, R. Bouyssou, T. Chevolleau, T. David, V. Arnal, S. Chhun, C. Monget, E. Richard, D. Galpin, J. Guillan, L. Arnaud, D. Roy, M. Guillermet, J. Ramard, O. Joubert, C. Verove","doi":"10.1109/IITC.2009.5090398","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090398","url":null,"abstract":"H2, O2, NH3 and CH4 in situ post-etching treatments (PET) have been investigated as a solution to prevent the residues formation (TiFx based) on TiN metallic hard mask (MHM) after etching in fluorocarbon based plasmas. The PET impact on the residues growth reduction on the mask and on the porous SiOCH modification is presented and discussed. The compatibility of the different PET is also evaluated for C045 dual damascene level using trench first MHM integration.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Thin low-k SiOC(N) dielectric / ruthenium stacked barrier technology 薄低k SiOC(N)介电/钌堆叠势垒技术
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090388
N. Tarumi, N. Oda, S. Kondo, S. Ogawa
{"title":"Thin low-k SiOC(N) dielectric / ruthenium stacked barrier technology","authors":"N. Tarumi, N. Oda, S. Kondo, S. Ogawa","doi":"10.1109/IITC.2009.5090388","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090388","url":null,"abstract":"A ruthenium (Ru) film was deposited by physical sputtering in an N2 atmosphere on a low-k SiOC dielectric film. This Ru deposition process modified the surface of the underlying low-k SiOC to a higher density SiOC(N) layer of approximately 3 nm thickness. This combined SiOC(N) / Ru stack showed good barrier properties without the need of any other barrier layer. This new stack structure removes the requirement for any TaN like film previously used to prevent Cu, Cu ion, and moisture diffusion into or from the SiOC film.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114473279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Novel scalable TDDB model for large-area MIM decoupling capacitors in high performance LSIs 高性能lsi中大面积MIM去耦电容的新型可扩展TDDB模型
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090385
N. Inoue, I. Kume, T. Iwaki, A. Shida, S. Yokogawa, M. Furumiya, Y. Hayashi
{"title":"Novel scalable TDDB model for large-area MIM decoupling capacitors in high performance LSIs","authors":"N. Inoue, I. Kume, T. Iwaki, A. Shida, S. Yokogawa, M. Furumiya, Y. Hayashi","doi":"10.1109/IITC.2009.5090385","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090385","url":null,"abstract":"Scalable TDDB model for large-area MIM capacitors is proposed to guarantee the reliability, limited by the defect-related extrinsic failure mode. Analysis based on this model leads to the guideline for the MIM design such as the dielectric thickness and capacitor area to achieve lifetime required for large decoupling capacitance on high-performance processors. Proposing TDDB model reveals that highly reliable MIM capacitor with ≫30 mm2, or ≫200 nF, per chip is realized successfully, suppressing the dynamic power-line noise in high performance LSIs.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125933229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM 用CD-SEM评价Cu/低k互连模式的线边缘粗糙度
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090394
A. Yamaguchi, D. Ryuzaki, K. Takeda, H. Kawada
{"title":"Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM","authors":"A. Yamaguchi, D. Ryuzaki, K. Takeda, H. Kawada","doi":"10.1109/IITC.2009.5090394","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090394","url":null,"abstract":"To establish the method for evaluating interconnect LER, resist, low-k, and Cu/low-k samples were observed and electric-field enhancement was simulated. Wedge-shape LER was observed in the edges of low-k and Cu/low-k patterns, and simulations showed that the wedge causes serious electric-field enhancement which can degrade TDDB property. To predict the risk of TDDB, inspections of the wedge angle after low-k etching and Cu CMP are required as well as that of the degree of LER.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"31 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125876477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Packaging characteristics of 6-layer ultra low-k/Cu dual damascene interconnect featuring advanced scalable porous silica (k=2.1) 采用先进可扩展多孔二氧化硅(k=2.1)的6层超低k/Cu双大马士革互连的封装特性
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090355
S. Chikaki, E. Soda, A. Gawase, T. Suzuki, Y. Kawashima, N. Oda, S. Saito
{"title":"Packaging characteristics of 6-layer ultra low-k/Cu dual damascene interconnect featuring advanced scalable porous silica (k=2.1)","authors":"S. Chikaki, E. Soda, A. Gawase, T. Suzuki, Y. Kawashima, N. Oda, S. Saito","doi":"10.1109/IITC.2009.5090355","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090355","url":null,"abstract":"To enhance the process damage tolerance, a 2nd generation scalable porous silica (k=2.1) has been developed by reducing pore-size to 2/3. Using this new low-k film, hybrid dual-damascene interconnects were successfully fabricated with low thermal stress and high adhesion strength. Packaging performance of the six-layered multilevel interconnects was also evaluated with wire-bonding and temperature-cycle tests.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123406987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Theoretical analyses of chemical reactions for forming hydrocarbon-bridged SiOCH low-k Films in PECVD processes PECVD工艺中烃类桥接SiOCH低钾膜形成化学反应的理论分析
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090357
N. Tajima, Y. Ohashi, S. Nagano, Y. Xu, S. Matsumoto, T. Kada, T. Ohno
{"title":"Theoretical analyses of chemical reactions for forming hydrocarbon-bridged SiOCH low-k Films in PECVD processes","authors":"N. Tajima, Y. Ohashi, S. Nagano, Y. Xu, S. Matsumoto, T. Kada, T. Ohno","doi":"10.1109/IITC.2009.5090357","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090357","url":null,"abstract":"The advantages of the SiOCH low-k films with hydrocarbon cross-links (hydrocarbon bridges) Si-Cn-Si have been reported recently. However, hydrocarbon cross-links are not produced so selectively by the PECVD method, since the hydrocarbon components tend to form terminal atom groups such as Si-CH3. For producing hydrocarbon cross-links effectively by the PECVD method, the polymerization reactions of SiOCH precursors in the PECVD process should be understood well. We have theoretically examined the bonding reactions of the atom groups of SiOCH compounds. By examining the reactions involving radicals and ions, it has been found that the radical species Si·, C·, and O· produce Si-O, C-Si, and O-Si bonds, respectively, while the ionic species produce Si-O bonds. These results suggest that the precursors should produce Si-Cn· radicals preferably for the effective production of the hydrocarbon cross-links.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131766583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Correlation between I–V slope and TDDB voltage acceleration for Cu/low-k interconnects Cu/低k互连中I-V斜率与TDDB电压加速度的相关性
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090382
F. Chen, J. Gambino, M. Shinosky, B. Li, O. Bravo, M. Angyal, D. Badami, J. Aitken
{"title":"Correlation between I–V slope and TDDB voltage acceleration for Cu/low-k interconnects","authors":"F. Chen, J. Gambino, M. Shinosky, B. Li, O. Bravo, M. Angyal, D. Badami, J. Aitken","doi":"10.1109/IITC.2009.5090382","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090382","url":null,"abstract":"In this paper, a correlation between the I–V slope at low fields and TDDB voltage acceleration is demonstrated for the first time, based on a wide range of data from 32nm to 130nm node hardware. The data supports the √E model, which is based on electron fluence (leakage current) driven, Cu catalyzed, low-k dielectric breakdown. Using this correlation, a fast wafer level screen method was also implemented for process improvement and TDDB reliability monitoring.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122280495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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