Correlation between I–V slope and TDDB voltage acceleration for Cu/low-k interconnects

Abstract

In this paper, a correlation between the I–V slope at low fields and TDDB voltage acceleration is demonstrated for the first time, based on a wide range of data from 32nm to 130nm node hardware. The data supports the √E model, which is based on electron fluence (leakage current) driven, Cu catalyzed, low-k dielectric breakdown. Using this correlation, a fast wafer level screen method was also implemented for process improvement and TDDB reliability monitoring.