2009 IEEE International Interconnect Technology Conference最新文献

Upstream electromigration study on multiple via structures in copper interconnect 铜互连多通孔结构的上游电迁移研究

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090347

M. Lin, N. Jou, James W. Liang, A. Juan, K. Su

引用次数: 4

Metrology of 3D IC with X-ray Microscopy and nano-scale X-ray CT 三维集成电路的x射线显微镜和纳米级x射线CT计量

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090362

Steve Wang, J. Gelb, S. H. Lau, W. Yun

引用次数: 5

A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER) 考虑尺寸效应和线边粗糙度的铜互连电阻率物理模型及实验测量

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090396

G. Lopez, J. Davis, J. Meindl

{"title":"A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER)","authors":"G. Lopez, J. Davis, J. Meindl","doi":"10.1109/IITC.2009.5090396","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090396","url":null,"abstract":"A new closed-form effective resistivity (rhoeff) model as a function of line-edge roughness (LER), sidewall specularity p, and grain boundary scattering R is presented. There is improved physical insight to increasing resistivity than previous models. The model is validated against former simulation data and calibrated with electrical measurements of fabricated Cu interconnect test structures exhibiting an average of 14 nm LER for line widths ranging from 61 nm to 332 nm. Upon fitting the new model to experimental data, p and R are determined to be 0 and 0.79, respectively. The model is also used to interpret ITRS 2007 projections for local wire resistivity. ITRS projections for resistivity can only be achieved with very high quality interconnect structures that have nearly elastic sidewall collisions (p=0.95), low grain reflectivity (R=0.40), and no line edge roughness (LER=0nm). In fact, adding 6.0nm of LER increases rhoeff by ~20% for 2022 (11nm node). Finally, a projection with pessimistic values of p=0, R=0.5 and LER=1.0nm predicts an 87% greater rhoeff value than the ITRS 2007 projection for the 11 nm node.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117329053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Evaluation of plasma damage in blanket and patterned low-k structures by near-field scanning probe microwave microscope: effect of plasma ash chemistry 用近场扫描探针微波显微镜评价等离子体对毛毯和图案低k结构的损伤:等离子体灰分化学的影响

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090363

A. Urbanowicz, V. V. Talanov, Marianna Pantouvaki, Herbert Struyf, S. Gendt, M. R. Baklanov

引用次数: 3

Conductance quantization of gold nanowires as a ballistic conductor 作为弹道导体的金纳米线的电导量子化

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090337

K. Takayanagi, Y. Oshima, Y. Kurui

引用次数: 3

Characterization of plasma damaged porous ULK SiCOH layers in aspect of changes in the diffusion behavior of solvents and repair-chemicals 等离子体损伤的多孔ULK SiCOH层在溶剂和修复化学物质扩散行为变化方面的表征

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090346

T. Oszinda, M. Schaller, D. Fischer, S. Schulz

引用次数: 1

Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM) 基于有限元法的片对片TSV结构应力敏感性分析

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090354

H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, A. Kawai, K. Arai, T. Suzuki, T. Nakamura, T. Ohba

引用次数: 15

Development of porous silica ultra low-k films for 32 nm-node interconnects and beyond 用于32nm及以上节点互连的多孔二氧化硅超低钾薄膜的研制

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090358

T. Yamazaki, M. Hirakawa, T. Nakayama, H. Murakami

引用次数: 2

Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing 低k互连堆栈与一种新颖的自对准通过图案工艺为32nm大批量生产

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090400

R. Brain, S. Agrawal, D. Becher, R. Bigwood, M. Buehler, V. Chikarmane, M. Childs, J. Choi, Shannon E. Daviess, C. Ganpule, Jun He, P. Hentges, I. Jin, S. Klopcic, G. Malyavantham, B. McFadden, J. Neulinger, J. Neirynck, Y. Neirynck, C. Pelto, P. Plekhanov, Y. Shusterman, T. Van, Martin Weiss, S. Williams, F. Xia, P. Yashar, A. Yeoh

{"title":"Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing","authors":"R. Brain, S. Agrawal, D. Becher, R. Bigwood, M. Buehler, V. Chikarmane, M. Childs, J. Choi, Shannon E. Daviess, C. Ganpule, Jun He, P. Hentges, I. Jin, S. Klopcic, G. Malyavantham, B. McFadden, J. Neulinger, J. Neirynck, Y. Neirynck, C. Pelto, P. Plekhanov, Y. Shusterman, T. Van, Martin Weiss, S. Williams, F. Xia, P. Yashar, A. Yeoh","doi":"10.1109/IITC.2009.5090400","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090400","url":null,"abstract":"Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration performance have been carefully balanced to meet the high reliability requirements while maintaining the lowest possible resistance. A new patterning scheme has been used to limit any patterning damage to the lower-k ILD and address the increasingly difficult problem of via-to-metal shorting at these very tight pitches. The interconnect stack has a thick Metal-9 layer to provide a low resistance path for the power and I/O routing that has been carefully scaled to maintain a low resistance. The combined interconnect stack provides high density, performance, and reliability, and supports a Pb-free 32nm process.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127756469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Challenges of Low Effective-K approaches for future Cu interconnect 低有效k方法对未来铜互连的挑战

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090329

T. Bao, H. Chen, C.J. Lee, H. Lu, H.W. Chen, H. Tsai, C.C. Lin, S. Jeng, S. Shue, C. Yu

引用次数: 1