发布求助
文献互助 智能选刊 最新文献

2009 IEEE International Interconnect Technology Conference最新文献

筛选
英文 中文
Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation LER对BEOL介质可靠性的影响:一个定量模型和实验验证
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090395
Z. Tokei, P. Roussel, M. Stucchi, J. Versluijs, I. Ciofi, L. Carbonell, G. Beyer, A. Cockburn, M. Agustin, K. Shah
{"title":"Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation","authors":"Z. Tokei, P. Roussel, M. Stucchi, J. Versluijs, I. Ciofi, L. Carbonell, G. Beyer, A. Cockburn, M. Agustin, K. Shah","doi":"10.1109/IITC.2009.5090395","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090395","url":null,"abstract":"For the first time we provide a model for describing the LER induced BEOL TDDB lifetime reduction. The model was validated on 50nm ½ pitch copper damascene lines embedded into a k=2.5 low-k material.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Reliable through silicon vias for 3D silicon applications 可靠的硅通孔，适用于3D硅应用
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090341
M. Shapiro, M. Interrante, P. Andry, B. Dang, C. Tsang, R. Liptak, J. Griffith, E. Sprogis, L. Guerin, V. Truong, D. Berger, J. Knickerbocker
{"title":"Reliable through silicon vias for 3D silicon applications","authors":"M. Shapiro, M. Interrante, P. Andry, B. Dang, C. Tsang, R. Liptak, J. Griffith, E. Sprogis, L. Guerin, V. Truong, D. Berger, J. Knickerbocker","doi":"10.1109/IITC.2009.5090341","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090341","url":null,"abstract":"The use of through silicon vias (TSVs) is required to implement 3D chip stacking technology. This work explores a method to fabricate highly reliable TSVs that is compatible with CMOS processing. The key feature of the TSVs is a redundant tungsten bar with a high temperature thermal oxide insulating liner. Care must be taken when exposing the TSVs from the back side so that material is not left on the surface that can cause a leakage path to the silicon wafer. TSVs were produced with that had no fails through standard JDEC testing.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124645347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Chip-packaging interaction in Cu/very low-k interconnect 铜/极低k互连中的芯片封装相互作用
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090366
Hsiu-Ping Wei, H. Tsai, Yu-Wen Liu, Hsien-Wei Chen, S. Jeng, Douglas C. H. Yu
{"title":"Chip-packaging interaction in Cu/very low-k interconnect","authors":"Hsiu-Ping Wei, H. Tsai, Yu-Wen Liu, Hsien-Wei Chen, S. Jeng, Douglas C. H. Yu","doi":"10.1109/IITC.2009.5090366","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090366","url":null,"abstract":"Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122852845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Interconnection with copper pillar bumps : Process and applications 铜柱凸点互连:工艺和应用
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090391
C. Lee
{"title":"Interconnection with copper pillar bumps : Process and applications","authors":"C. Lee","doi":"10.1109/IITC.2009.5090391","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090391","url":null,"abstract":"Flipchip technologies have been evolved to grab the major portion of the high and medium performance markets, where the bump interconnections are required. Bumps can be diverse in their contents, that is, binary, ternary, etc.. The most popular alloy is SnPb (eutectic), while the environmental importance pushes the market to adapt the green solution where SnAg or SnCu can be one of the choice. Considering the electrical performance including electro-migration effect and simplicity of the process, Cu bumps is chosen to be an alternative. In this presentation, the Cu pillar bump will be introduced embracing the fine pitch (less than 50 um) process and applications.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Resist planarization for trench first dual damascene 抵抗平面化为壕沟第一双大马士革
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090351
H. Chibahara, H. Korogi, Y. Ono, T. Saito, K. Yoshikawa, K. Yonekura, T. Furuhashi, K. Tomita, H. Sakaue, A. Ueki, S. Matsumoto, Moriaki Akazawa, H. Miyatake
{"title":"Resist planarization for trench first dual damascene","authors":"H. Chibahara, H. Korogi, Y. Ono, T. Saito, K. Yoshikawa, K. Yonekura, T. Furuhashi, K. Tomita, H. Sakaue, A. Ueki, S. Matsumoto, Moriaki Akazawa, H. Miyatake","doi":"10.1109/IITC.2009.5090351","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090351","url":null,"abstract":"Resist planarization is applied to trench first dual damascene process in order to enhance focus margin for via lithography after hard mask etch. As a planarization process, resist CMP is better than conventional resist etch back, However, hard mask (HM) erosion by resist CMP causes serious problem of lessened thickness of Cu. To solve it, the combination of CMP and etch back (C+E) is adopted. This method realizes enhancement of the focus margin and prevention from the hard mask erosion at the same time.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130219946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability failure modes in interconnects for the 45 nm technology node and beyond 45纳米及以上技术节点互连的可靠性失效模式
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090381
L. Arnaud, D. Galpin, S. Chhun, C. Monget, E. Richard, D. Roy, C. Besset, M. Vilmay, L. Doyen, P. Waltz, E. Petitprez, F. Terrier, G. Imbert, Y. Le Friec
{"title":"Reliability failure modes in interconnects for the 45 nm technology node and beyond","authors":"L. Arnaud, D. Galpin, S. Chhun, C. Monget, E. Richard, D. Roy, C. Besset, M. Vilmay, L. Doyen, P. Waltz, E. Petitprez, F. Terrier, G. Imbert, Y. Le Friec","doi":"10.1109/IITC.2009.5090381","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090381","url":null,"abstract":"This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45 nm node thanks to fine optimizations of Cu barriers, Cu filling, and ULK surface quality.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123751126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electrode and substrate contacts in carbon nanofiber interconnects 碳纳米纤维互连中的电极和衬底接触
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090360
Tsutomu Saito, H. Yabutani, Toshishige Yamada, P. Wilhite, Cary Y. Yang
{"title":"Electrode and substrate contacts in carbon nanofiber interconnects","authors":"Tsutomu Saito, H. Yabutani, Toshishige Yamada, P. Wilhite, Cary Y. Yang","doi":"10.1109/IITC.2009.5090360","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090360","url":null,"abstract":"To study the reliability of carbon nanofiber (CNF) interconnect under high-current stress, electrical and thermal transports across CNF-electrode interfaces and between electrodes are considered. For this investigation, three different types of contacts are examined: (a) CNF-Au electrode, (b) CNF-SiO2 substrate, and (c) tungsten-deposited CNF-Au electrode. We have determined that contact (c) improves the overall electrical and thermal transport characteristics of the system.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124657203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advanced Direct-CMP process for porous low-k thin film 多孔低钾薄膜的先进直接- cmp工艺
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090399
H. Korogi, H. Chibahara, Shigeru Suzuki, M. Tsutsue, K. Seo, Y. Oka, K. Goto, Moriaki Akazawa, H. Miyatake, S. Matsumoto, T. Ueda
{"title":"Advanced Direct-CMP process for porous low-k thin film","authors":"H. Korogi, H. Chibahara, Shigeru Suzuki, M. Tsutsue, K. Seo, Y. Oka, K. Goto, Moriaki Akazawa, H. Miyatake, S. Matsumoto, T. Ueda","doi":"10.1109/IITC.2009.5090399","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090399","url":null,"abstract":"In order to reduce the effective dielectric constant (keff) for the 32 nm technology node and beyond, Direct-CMP of a porous low-k film without a protective cap layer is required. However, the degradation of breakdown electric field (Ebd) has been one of critical issues. This study clarified that the Ebd degradation was caused by the pit defects on the surface of porous low-k film during Direct-CMP. In order to suppress the pit defects, we evaluated dependency of micro-pores density of CMP pads. As a result, we demonstrated that CMP pads with low-density micro-pores drastically reduced them and improved the Ebd degradation. In this paper, the mechanism for their reduction is also discussed.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129179627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations 30纳米以下互连的金属化:不同衬里/种子组合的比较
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090387
L. Carbonell, H. Volders, N. Heylen, K. Kellens, R. Caluwaerts, K. Devriendt, E. Sanchez, J. Wouters, V. Gravey, K. Shah, Qian Luo, A. Sundarrajan, J. Lu, J. Aubuchon, P. Ma, M. Narasimhan, A. Cockburn, Z. Tokei, G. Beyer
{"title":"Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations","authors":"L. Carbonell, H. Volders, N. Heylen, K. Kellens, R. Caluwaerts, K. Devriendt, E. Sanchez, J. Wouters, V. Gravey, K. Shah, Qian Luo, A. Sundarrajan, J. Lu, J. Aubuchon, P. Ma, M. Narasimhan, A. Cockburn, Z. Tokei, G. Beyer","doi":"10.1109/IITC.2009.5090387","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090387","url":null,"abstract":"Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126677470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fabrication of 70-nm-diameter carbon nanotube via interconnects by remote plasma-enhanced chemical vapor deposition and their electrical properties 远距离等离子体增强化学气相沉积制备直径70纳米的碳纳米管及其电学性能
2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI: 10.1109/IITC.2009.5090336
M. Katagiri, Y. Yamazaki, N. Sakuma, Mariko Suzuki, T. Sakai, M. Wada, N. Nakamura, N. Matsunaga, Shintaro Sato, M. Nihei, Y. Awano
{"title":"Fabrication of 70-nm-diameter carbon nanotube via interconnects by remote plasma-enhanced chemical vapor deposition and their electrical properties","authors":"M. Katagiri, Y. Yamazaki, N. Sakuma, Mariko Suzuki, T. Sakai, M. Wada, N. Nakamura, N. Matsunaga, Shintaro Sato, M. Nihei, Y. Awano","doi":"10.1109/IITC.2009.5090336","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090336","url":null,"abstract":"We have succeeded in fabricating ultrafine carbon nanotube (CNT) via interconnects with SiOC interlayer dielectrics. High-quality multiwalled CNTs are grown in via holes with a diameter of 70 nm using pulse-exited remote plasma-enhanced chemical vapor deposition at 450 °C. The resistance of a 70-nm-diameter CNT via is 52 Ω, which is the lowest ever reported for CNT via interconnects. The CNT via interconnect has the capability to sustain current density as high as 1×108 A/cm2.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115082792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信