M. Shapiro, M. Interrante, P. Andry, B. Dang, C. Tsang, R. Liptak, J. Griffith, E. Sprogis, L. Guerin, V. Truong, D. Berger, J. Knickerbocker
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Reliable through silicon vias for 3D silicon applications
The use of through silicon vias (TSVs) is required to implement 3D chip stacking technology. This work explores a method to fabricate highly reliable TSVs that is compatible with CMOS processing. The key feature of the TSVs is a redundant tungsten bar with a high temperature thermal oxide insulating liner. Care must be taken when exposing the TSVs from the back side so that material is not left on the surface that can cause a leakage path to the silicon wafer. TSVs were produced with that had no fails through standard JDEC testing.
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