Hsiu-Ping Wei, H. Tsai, Yu-Wen Liu, Hsien-Wei Chen, S. Jeng, Douglas C. H. Yu
{"title":"铜/极低k互连中的芯片封装相互作用","authors":"Hsiu-Ping Wei, H. Tsai, Yu-Wen Liu, Hsien-Wei Chen, S. Jeng, Douglas C. H. Yu","doi":"10.1109/IITC.2009.5090366","DOIUrl":null,"url":null,"abstract":"Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Chip-packaging interaction in Cu/very low-k interconnect\",\"authors\":\"Hsiu-Ping Wei, H. Tsai, Yu-Wen Liu, Hsien-Wei Chen, S. Jeng, Douglas C. H. Yu\",\"doi\":\"10.1109/IITC.2009.5090366\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.\",\"PeriodicalId\":301012,\"journal\":{\"name\":\"2009 IEEE International Interconnect Technology Conference\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Interconnect Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2009.5090366\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Interconnect Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2009.5090366","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Chip-packaging interaction in Cu/very low-k interconnect
Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.
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