F. Inoue, T. Yokoyama, S. Tanaka, K. Yamamoto, M. Koyanagi, T. Fukushima, Z. Wang, S. Shingubara
{"title":"Study of low resistance TSV using electroless plated copper and tungsten-alloy barrier","authors":"F. Inoue, T. Yokoyama, S. Tanaka, K. Yamamoto, M. Koyanagi, T. Fukushima, Z. Wang, S. Shingubara","doi":"10.1109/IITC.2009.5090376","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090376","url":null,"abstract":"We studied a low temperature deposition of tungsten-alloy barrier and copper layers only by electroless plating, with an aim of realizing low resistance TSV with a high aspect ratio. We succeeded in successive deposition of W-Ni-P barrier layer and Cu on SiO2. Furthermore, we found that the addition of Cl ions to SPS- and PEG- plating bath significantly improved the conformal deposition property even for a few μm in diameter TSVs with the aspect ratio higher than 10.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114505911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Asami, T. Owada, S. Akiyama, N. Ohara, Y. Iba, T. Kouno, H. Kudo, S. Takesako, T. Osada, T. Kirimura, H. Watatani, A. Uedono, Y. Nara, M. Kase
{"title":"Novel low-k SiOC (k=2.4) with superior tolerance to direct polish and ashing for advanced BEOL integration","authors":"N. Asami, T. Owada, S. Akiyama, N. Ohara, Y. Iba, T. Kouno, H. Kudo, S. Takesako, T. Osada, T. Kirimura, H. Watatani, A. Uedono, Y. Nara, M. Kase","doi":"10.1109/IITC.2009.5090373","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090373","url":null,"abstract":"We established novel SiOC (k=2.4) with higher process damage tolerance. The SiOC was deposited using organo-silane with acetylene bond as a precursor of plasma enhanced chemical vapor deposition (PECVD). The precursor takes high concentration of carbon in the SiOC and the SiOC has closed pores since deposited without using any porogens, therefore lower damage by ashing and direct Cu polish are achieved. We fabricated Cu wirings using direct polish. We confirmed that dielectric constant of the SiOC did not increase after ashing and direct polish process and maintained k=2.4.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123624029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. H. Teh, R. Caramto, S. Arkalgud, T. Saito, K. Maruyama, K. Maekawa
{"title":"Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration","authors":"W. H. Teh, R. Caramto, S. Arkalgud, T. Saito, K. Maruyama, K. Maekawa","doi":"10.1109/IITC.2009.5090338","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090338","url":null,"abstract":"We aim to fill the processing gap in 300 mm wafer-scale non-Bosch TSV etch process by developing production-worthy TSV etch solutions for logic-centric 3D integration. This is based on a magnetically-enhanced capacitively-coupled plasma (CCP) etching system. Key factors in this system that contribute to the control of via features such as global sidewall tapering, local sidewall roughness, Si etch rates, mask undercutting and local bowing effects were evaluated. The etching characteristics of anisotropic vias in silicon with nominal feature sizes of, but not limited to 5 µm × 25 µm (AR ∼ 5) and 1 µm × 20 µm (AR ∼ 20) with minimum pitches of 5 µm and 1 µm, respectively were quantified. 3 µm × 14 µm and 5 µm × 19 µm Cu-filled TSV are demonstrated by having continuous 2kÅ TEOS oxide liner/100 nm Ta(TaN) barrier/2kÅ Cu seed stack enabled by TSV etch.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129808471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Seo, Chih-Chao Yang, C. Yeh, B. Haran, D. Horak, S. Fan, C. Koburger, D. Canaperi, S. P. Papa Rao, F. Monsieur, A. Knorr, A. Kerber, Chao-Kun Hu, J. Kelly, T. Vo, J. Cummings, Matthew Smalleya, K. Petrillo, S. Mehta, S. Schmitz, T. Levin, Dae-gyu Park, J. Stathis, T. Spooner, V. Paruchuri, J. Wynne, D. Edelstein, D. Mcherron, B. Doris
{"title":"Copper contact metallization for 22 nm and beyond","authors":"S. Seo, Chih-Chao Yang, C. Yeh, B. Haran, D. Horak, S. Fan, C. Koburger, D. Canaperi, S. P. Papa Rao, F. Monsieur, A. Knorr, A. Kerber, Chao-Kun Hu, J. Kelly, T. Vo, J. Cummings, Matthew Smalleya, K. Petrillo, S. Mehta, S. Schmitz, T. Levin, Dae-gyu Park, J. Stathis, T. Spooner, V. Paruchuri, J. Wynne, D. Edelstein, D. Mcherron, B. Doris","doi":"10.1109/IITC.2009.5090326","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090326","url":null,"abstract":"We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate world's smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128669358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Isobayashi, J. Kelly, Takeshi Watanabe, M. Fujiwara, C. Koburger, J. Maniscalco, T. Vo, S. Chiang, Ja Ren, T. Spooner, M. Takayanagi, T. Usui, K. Ishimaru
{"title":"Robust and low cost copper contact application for low power device at 32 nm-Node and beyond","authors":"A. Isobayashi, J. Kelly, Takeshi Watanabe, M. Fujiwara, C. Koburger, J. Maniscalco, T. Vo, S. Chiang, Ja Ren, T. Spooner, M. Takayanagi, T. Usui, K. Ishimaru","doi":"10.1109/IITC.2009.5090325","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090325","url":null,"abstract":"We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper along the contact hole with the sufficiently wide gap opening at the top by the use of the directional sputtering and the re-sputtering techniques. In addition, this process was implemented on fully integrated 32 nm-node device wafers and the optimized process produced sufficient performance to meet 32 nm-node requirements. The investigation also included two cases with intentional departure from the optimal conditions, one with a low thickness barrier and the other without copper re-sputtering. In both cases negative influence on front-end-of-the-line (FEOL) parameters was observed.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115815849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Nakamura, Y. Takigawa, E. Soda, N. Hosoi, Y. Tarumi, H. Aoyama, Y. Tanaka, D. Kawamura, S. Ogawa, N. Oda, S. Kondo, I. Mori, S. Saito
{"title":"Design impact study of wiring size and barrier metal on device performance toward 22 nm-node featuring EUV lithography","authors":"N. Nakamura, Y. Takigawa, E. Soda, N. Hosoi, Y. Tarumi, H. Aoyama, Y. Tanaka, D. Kawamura, S. Ogawa, N. Oda, S. Kondo, I. Mori, S. Saito","doi":"10.1109/IITC.2009.5090328","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090328","url":null,"abstract":"The resistance of wiring with a width of less than 40 nm was firstly evaluated by using an EUV lithography (λ=13.5 nm). The resistance was quite high in narrow wiring with conventional Ta barrier film, while a very low effective resistivity ρeff of lower than 4.5 µΩ cm was obtained by using PVD-Ru barrier film. This difference was attributed to combination of thinner barrier metal films in the trench, the larger grain size and better filling capability of the Ru barrier metal. The predicted circuit-performance using the Ru barrier was 10% higher than that with Ta barrier and the operating-speed distribution was estimated to be less than 5 % for the 22nm-node CMOS generation.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125680532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Matsumoto, K. Neishi, H. Itoh, H. Sato, S. Hosaka, J. Koike
{"title":"Deposition behavior and diffusion barrier property of CVD MnOx","authors":"K. Matsumoto, K. Neishi, H. Itoh, H. Sato, S. Hosaka, J. Koike","doi":"10.1109/IITC.2009.5090386","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090386","url":null,"abstract":"Chemical vapor deposition of MnOx (CVD-MnO<inf>x</inf>) was performed on blanket substrates as well as patterned interconnect structures. A conformal layer of MnO<inf>x</inf> was formed by the MnO<inf>x</inf> on SiO<inf>2</inf> within a contact hole with a uniform thickness of 3 to 4 nm. Excellent diffusion barrier property was obtained after annealing at 400 °C. In contrast, the CVD-MnO<inf>x</inf> on Cu formed solid solution with Cu. The solute Mn was migrated towards the interface of Cu/SiO<inf>2</inf> to form MnO<inf>x</inf>.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"543 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132415416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated digital AV platform “UniPhier“","authors":"S. Fujikawa","doi":"10.1109/IITC.2009.5090324","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090324","url":null,"abstract":"Panasonic is promoting development of the integrated digital AV platform “UniPhier (Universal Platform for High-quality Image Enhancing Revolution)” aiming to apply in a wide range of digital CE field from home-use AV devices to mobile phones. Most of Panasonic digital CE products, such as digital TVs, DVD/Blu-ray recorders and mobile Phones, are now the UniPhier based products. The UniPhier is not simply a design infrastructure but also the means by which we can build an integrated capability.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122236644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Aarts, M. Bariatto, A. Fontes, H. Neves, S. Kisban, P. Ruther, J. Penders, C. Bartic, K. Verstreken, C. van Hoof
{"title":"Building the human-chip interface","authors":"A. Aarts, M. Bariatto, A. Fontes, H. Neves, S. Kisban, P. Ruther, J. Penders, C. Bartic, K. Verstreken, C. van Hoof","doi":"10.1109/IITC.2009.5090332","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090332","url":null,"abstract":"This paper summarizes several interconnection issues related to brain-computer interfaces and neuroprosthetics. Silicon-based out-of-plane integration and interconnection to achieve partially-invasive brain-computer interfaces will be described.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134332189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Mertens, T-G. Kim, M. Claes, Q. Le, G. Vereecke, E. Kesters, S. Suhard, A. Pacco, M. Lux, K. Kenis, A. Urbanowicz, Z. Tokei, G. Beyer
{"title":"Challenges and novel approaches for photo resist removal and post-etch residue removal for 22 nm interconnects","authors":"P. Mertens, T-G. Kim, M. Claes, Q. Le, G. Vereecke, E. Kesters, S. Suhard, A. Pacco, M. Lux, K. Kenis, A. Urbanowicz, Z. Tokei, G. Beyer","doi":"10.1109/IITC.2009.5090397","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090397","url":null,"abstract":"The critical challenges of removal of post metal hard mask etch photo resist removal and post low-k etch residue removal are described. An overview of some new non-plasma based approaches is presented.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"928 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}