Cu/低k互连中I-V斜率与TDDB电压加速度的相关性

2009 IEEE International Interconnect Technology Conference Pub Date : 2009-06-01 DOI:10.1109/IITC.2009.5090382

F. Chen, J. Gambino, M. Shinosky, B. Li, O. Bravo, M. Angyal, D. Badami, J. Aitken

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引用次数: 4

摘要

本文基于从32nm到130nm节点硬件的广泛数据，首次证明了低场I-V斜率与TDDB电压加速度之间的相关性。数据支持基于电子影响(泄漏电流)驱动、Cu催化、低k介电击穿的√E模型。利用这种相关性，还实现了一种快速晶圆级筛选方法，用于工艺改进和TDDB可靠性监测。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Correlation between I–V slope and TDDB voltage acceleration for Cu/low-k interconnects

In this paper, a correlation between the I–V slope at low fields and TDDB voltage acceleration is demonstrated for the first time, based on a wide range of data from 32nm to 130nm node hardware. The data supports the √E model, which is based on electron fluence (leakage current) driven, Cu catalyzed, low-k dielectric breakdown. Using this correlation, a fast wafer level screen method was also implemented for process improvement and TDDB reliability monitoring.

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2009 IEEE International Interconnect Technology Conference

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