IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)最新文献_第3页

Methods to reduce radiation from split ground plane structures [packaging] 减少劈裂地平面结构辐射的方法[封装]

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819226

T. E. Moran, K.L. Virga, G. Aguirre, J. Prince

引用次数: 21

Distributed effects of a gap in power/ground planes 电源/地平面间隙的分布效应

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819227

D. Duan, B. Rubin, J. Magerlein

引用次数: 14

Modeling and transient simulation of planes in electronic packages for GHz systems GHz系统电子封装中平面的建模和瞬态仿真

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819214

N. Na, M. Swaminathan

引用次数: 23

Interconnect limits on gigascale integration 千兆级集成的互连限制

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.7567/SSDM.1999.P-2

J. Meindl

{"title":"Interconnect limits on gigascale integration","authors":"J. Meindl","doi":"10.7567/SSDM.1999.P-2","DOIUrl":"https://doi.org/10.7567/SSDM.1999.P-2","url":null,"abstract":"Summary form only given. From the inception of microelectronics in 1959 until the early 1990s, transistors dominated both IC performance and cost, while interconnects were of secondary importance. In recent years, this hegemony has largely dissipated. Interconnects have become critical determinants of IC performance and cost. The nature of this shift can be illustrated by the fact that for late 1980s 1 /spl mu/m technology, the intrinsic switching delay of an unloaded MOSFET approaches 10 ps while 1 mm interconnect response time is approximately 1 ps, but for early 2000 0.1 /spl mu/m technology, intrinsic MOSFET delay decreases to about 1 ps, while 1 mm interconnect response time increases to 100 ps. The latency of a 1 mm interconnect devolves from one decade faster to two decades slower than transistor delay. Concurrent with this signal wiring dilemma, clock frequency is increasing by 100/spl times/ placing stringent new demands on the chip clock distribution network interconnects. Supply current is increasing by 60/spl times/ while supply voltage scales downward by 5/spl times/, imposing a huge new burden on the power distribution network interconnects. Maximum total wire length per chip increases by 50/spl times/, and chip-to-package I/O interconnect count increases by 10-20/spl times/. Early 21st century opportunities for GSI will thus be governed by an interconnect dominated hierarchy of theoretical and practical limits whose five levels are codified as fundamental, material, device, circuit and system. Systematic exploration of this hierarchy of limits reveals salient opportunities to address the interconnect problem.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121158494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Noise measurements on Power4 Test chip 在Power4测试芯片上的噪声测量

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819186

A. Haridass, N. James, B. McCredie

引用次数: 0

Study of meander line delay in circuit boards 线路板中曲线延迟的研究

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819224

B. Rubin, B. Singh

引用次数: 80

Latency insertion method for the fast simulation of interconnection networks 互连网络快速仿真的延迟插入方法

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819237

J. Schutt-Ainé

引用次数: 0

Equivalent circuit modeling of single and coupled on-chip interconnects on lossy silicon substrate 损耗硅衬底上单片和耦合片上互连的等效电路建模

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819222

Ji Zheng, Y. Hahm, A. Weisshaar, V. K. Tripathi

引用次数: 11

Power distribution modeling and decoupling of multilayer printed circuit board 多层印刷电路板的功率分布建模与解耦

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819203

J. Bandyopadhyay

引用次数: 12

High-performance silicon MMIC interconnect for millimeter wave wireless communication 用于毫米波无线通信的高性能硅MMIC互连

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819233

Juno Kim, Y. Qian, Guojin Feng, P. Ma, M. Chang, T. Itoh

引用次数: 6