多层印刷电路板的功率分布建模与解耦

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819203

J. Bandyopadhyay

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引用次数: 12

摘要

对于电路板/卡设计人员来说，确定合适的去耦电容器的数量和值一直是一个具有挑战性的问题。缺乏适当的分析会导致保守或激进的设计。本文提出了一种方法，通过详细的板建模来确定卡/板的去耦电容器的正确数量和位置。举例说明了去耦电容在降低IBM RS/6000机器中使用的带有PowerPCT/sup TM/处理器的多层CPU卡的诱导dI/dt噪声方面的效果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Power distribution modeling and decoupling of multilayer printed circuit board

Determining the proper number and value of decoupling capacitors for boards/cards is always a challenging issue for board/card designers. Lack of proper analysis leads to either conservative or aggressive design. This paper presents a methodology for determining the right number and location of decoupling capacitors for a card/board through detailed board modeling. An example has been provided to demonstrate the effect of decoupling capacitors in reducing induced dI/dt noise for a multilayer CPU card with PowerPCT/sup TM/ processor used in IBM's RS/6000 machine.

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IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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