IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)最新文献

On the chicken-and-egg problem of determining the effect of crosstalk on delay in integrated circuits 确定集成电路中串扰对延迟影响的先有鸡还是先有蛋问题

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-12-01 DOI: 10.1109/EPEP.1999.819235

S. Sapatnekar

引用次数: 18

Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool 精确的芯片和封装三维电容模拟现实的互连使用通用fem工具

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819205

A. Hieke

引用次数: 1

Numerical analysis of surface waves on a grounded dielectric plane using the finite difference time domain method 用时域有限差分法对接地介质表面波进行数值分析

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819201

C. Schuster, W. Fichtner

引用次数: 2

Simultaneous switch noise and power plane bounce for CMOS technology CMOS技术的开关噪声和功率平面反弹

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819217

L. Smith

{"title":"Simultaneous switch noise and power plane bounce for CMOS technology","authors":"L. Smith","doi":"10.1109/EPEP.1999.819217","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819217","url":null,"abstract":"The simultaneous switch noise (SSN) problem has traditionally been thought of as an inductance problem. When many drivers on a Si chip switch at the same time, current crowds into the chip ground or V/sub dd/ inductance. Ground bounce occurs proportional to the inductance in the ground or V/sub dd/ lead and the rate of change of current. This line of thinking has been effective at solving SSN problems for lead frame packages. However, packaging has progressed to packages with power and ground planes. Package traces behave more like transmission lines with impedance and delay rather than lumped inductors. The signal waveform rise and fall times are so fast that an edge may fit within the package. Wire bonds have been replaced by solder bumps and peripheral leads have been replaced by solder balls. The new structures may have less than 1% of the inductance of the packages in use just a few years ago. Capacitive and resistive elements have been added to inductance matrices to account for the package time delay and losses, but the number of circuit elements in an SSN analysis and the increased number of simultaneously switching drivers have resulted in large, complex simulation runs that require much CPU time and computer resources. It has become harder to find meaningful model to hardware correlation for large SSN problems. It is time to consider a radically new approach to simulating the SSN problem. This paper looks at treatment of the SSN problem as a power plane bounce problem.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129925251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

Validation of integrated capacitor-via-planes model 集成电容平面模型的验证

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819207

Yuan-liang Li, D. Figueroa, T. Yew, C. Chung

{"title":"Validation of integrated capacitor-via-planes model","authors":"Yuan-liang Li, D. Figueroa, T. Yew, C. Chung","doi":"10.1109/EPEP.1999.819207","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819207","url":null,"abstract":"As clock speeds increase into the GHz regime and rise times decrease into the picosecond regime, the interaction between capacitors and the power/ground planes of the package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self inductance of the capacitor. In some cases, it even reduces the total effective loop inductance. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitors. The predicted results matched very well with measured data which give a high confidence on this predicting model and demonstrate the importance of modeling the interaction between capacitors, vias, and planes.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125309947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Electrical characterization of S/390 MCM packages from S-parameter measurements below 3 GHz 3 GHz以下S参数测量S/390 MCM封装的电气特性

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819197

F. Ktata, U. Arz, H. Grabinski

引用次数: 3

Accuracy considerations of power-ground plane models 电源-地平面模型的精度考虑

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819215

I. Novak

引用次数: 16

Simulation of embedded RF circuits using macromodels and synthesized equivalent circuits 利用宏模型和合成等效电路对嵌入式射频电路进行仿真

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819234

K. Choi, M. Swaminathan

引用次数: 2

Parameter extraction for circuit models of electronic packages without optimization 未经优化的电子封装电路模型参数提取

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819196

Luc Martens, S. Sercu

引用次数: 4

Improved global rational approximation macromodeling algorithm for transient simulation of interconnects 基于改进全局有理逼近的互联暂态仿真宏建模算法

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819199

M. Elzinga, K. Virga, J. Prince

引用次数: 1