精确的芯片和封装三维电容模拟现实的互连使用通用fem工具

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819205

A. Hieke

{"title":"精确的芯片和封装三维电容模拟现实的互连使用通用fem工具","authors":"A. Hieke","doi":"10.1109/EPEP.1999.819205","DOIUrl":null,"url":null,"abstract":"This paper describes on- and off-chip 3D capacitance simulations utilizing the ANSYS-Multiphysics/sup TM/ general purpose FEM system extended with an APDL macro for capacitance simulations. This facilitates the use of the advanced 3D capabilities of ANSYS/sup TM/ to generate, edit and visualize realistically shaped 3D structures.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool\",\"authors\":\"A. Hieke\",\"doi\":\"10.1109/EPEP.1999.819205\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes on- and off-chip 3D capacitance simulations utilizing the ANSYS-Multiphysics/sup TM/ general purpose FEM system extended with an APDL macro for capacitance simulations. This facilitates the use of the advanced 3D capabilities of ANSYS/sup TM/ to generate, edit and visualize realistically shaped 3D structures.\",\"PeriodicalId\":299335,\"journal\":{\"name\":\"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.1999.819205\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1999.819205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文描述了利用ANSYS-Multiphysics/sup TM/通用有限元系统扩展APDL宏进行电容仿真的片上和片外三维电容仿真。这有助于使用ANSYS/sup TM/的先进3D功能来生成，编辑和可视化逼真形状的3D结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool

This paper describes on- and off-chip 3D capacitance simulations utilizing the ANSYS-Multiphysics/sup TM/ general purpose FEM system extended with an APDL macro for capacitance simulations. This facilitates the use of the advanced 3D capabilities of ANSYS/sup TM/ to generate, edit and visualize realistically shaped 3D structures.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

自引率

0.00%

发文量