Validation of integrated capacitor-via-planes model

Abstract

As clock speeds increase into the GHz regime and rise times decrease into the picosecond regime, the interaction between capacitors and the power/ground planes of the package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self inductance of the capacitor. In some cases, it even reduces the total effective loop inductance. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitors. The predicted results matched very well with measured data which give a high confidence on this predicting model and demonstrate the importance of modeling the interaction between capacitors, vias, and planes.