IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)最新文献

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An integrated environment for the simulation of electrical, thermal and electromagnetic interactions in high-performance integrated circuits 用于模拟高性能集成电路中的电、热和电磁相互作用的集成环境
H. Gutierrez, C. Christoffersen, M. Steer
{"title":"An integrated environment for the simulation of electrical, thermal and electromagnetic interactions in high-performance integrated circuits","authors":"H. Gutierrez, C. Christoffersen, M. Steer","doi":"10.1109/EPEP.1999.819229","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819229","url":null,"abstract":"Joint computer simulation of circuit, thermal and electromagnetic interactions in high performance integrated circuits and systems is of particular importance for the modeling of electronic packaging, since packages are complex coupled systems where all of these aspects interact in a dynamic sense. This paper describes a computer environment that supports the simultaneous simulation of thermal, electromagnetic and circuit interactions in complex microwave circuits. Locally referenced modules have been used to enable disparate modeling tools to interact, and suggest possible paths to include mechanical interactions in the future. Two methods are presented for the simulation of electro-thermal interaction. The first is based on coupling of electrical and thermal environments using a lumped-parameter model of the heat dissipation dynamics. The second technique, consisting of the run-time coupling of a circuit simulator and a finite-element thermal solver, is based on an application program interface (API) that synchronizes the transfer of information between the two. Through this technique, simultaneous simulation of electrical, thermal and electromagnetic interactions has been achieved.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"48 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Limitations due to systematic phase errors on the extraction of loss tangent from micron-sized transmission line test structures 系统相位误差对微米级传输线测试结构中损耗正切提取的限制
R. Friar, D. Neikirk
{"title":"Limitations due to systematic phase errors on the extraction of loss tangent from micron-sized transmission line test structures","authors":"R. Friar, D. Neikirk","doi":"10.1109/EPEP.1999.819195","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819195","url":null,"abstract":"When two-port S-parameters are used to characterize microstrip test structures, finite phase measurement precision and small reference plane offsets can significantly limit the ability to extract the loss tangent from transmission lines with finite series resistance.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125116511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Domain decomposition approach for capacitance computation of non-orthogonal interconnect structures 非正交互连结构电容计算的区域分解方法
V. Veremey, R. Mittra
{"title":"Domain decomposition approach for capacitance computation of non-orthogonal interconnect structures","authors":"V. Veremey, R. Mittra","doi":"10.1109/EPEP.1999.819198","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819198","url":null,"abstract":"In this paper, we apply the domain decomposition approach in conjunction with the finite difference (FD) method to compute, efficiently, the capacitance matrices of crossovers and via type interconnect structures formed by traces that are nonorthogonal in general. In the past, we have applied the FD method in conjunction with the perfectly matched layer (PML) and the impedance boundary condition for FD mesh truncation, to compute the capacitances of orthogonal interconnect configurations. In this work, we extend the above approach to apply to more general geometries, e.g. vias and crossovers with arbitrary angles. The paper presents some representative numerical results and examines the convergence and efficiency issues of the proposed algorithm.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132595795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Radiated emission from pin-fin heat sink mounted on an EBGA package 安装在EBGA封装上的鳍片散热器的辐射发射
P. Qu, M. Iyer, Y. Qiu
{"title":"Radiated emission from pin-fin heat sink mounted on an EBGA package","authors":"P. Qu, M. Iyer, Y. Qiu","doi":"10.1109/EPEP.1999.819225","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819225","url":null,"abstract":"In this paper, radiated emissions from a commercial pin fin heat sink mounted on an EBGA package were studied. The effect of the pin length of the heat sink on the radiated field was analyzed. Finally, the mechanism of radiation enhancement was investigated, both from electromagnetic field and circuit points of view.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"80 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114105572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
RF characterization of low cost MCM-D substrates, manufactured on large area panels 在大面积面板上制造的低成本MCM-D基板的射频特性
D. Cottet, M. Scheffler, J. Grzyb, B. Oswald, G. Troster
{"title":"RF characterization of low cost MCM-D substrates, manufactured on large area panels","authors":"D. Cottet, M. Scheffler, J. Grzyb, B. Oswald, G. Troster","doi":"10.1109/EPEP.1999.819206","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819206","url":null,"abstract":"This article presents the RF characterization results of a large-area MCM-D technology developed within the EU LAP project. Microstrip lines were simulated, designed, and manufactured in several material combinations. Measurements up to 120 GHz showed good coincidence between simulation and reality. Future work is dedicated to filters and antennas in the 77 GHz range.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124706101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling of simultaneous switching output by equivalent source impedance 等效源阻抗的同步开关输出建模
R. Lutz, A. Weisshaar, V. Tripathi, T. Arabi, A. Lee
{"title":"Modeling of simultaneous switching output by equivalent source impedance","authors":"R. Lutz, A. Weisshaar, V. Tripathi, T. Arabi, A. Lee","doi":"10.1109/EPEP.1999.819218","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819218","url":null,"abstract":"A new technique for extracting an equivalent source impedance of simultaneous switching outputs (SSOs) from time domain data is presented. Simulation results for two test structures show good agreement between the waveforms at the receiver for the SSO outputs and the corresponding SSO equivalent source model.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Asymptotically zero power dissipation gigahertz clock distribution networks 渐近零功耗千兆赫时钟分配网络
P. Zarkesh-Ha, J. Meindl
{"title":"Asymptotically zero power dissipation gigahertz clock distribution networks","authors":"P. Zarkesh-Ha, J. Meindl","doi":"10.1109/EPEP.1999.819193","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819193","url":null,"abstract":"A novel global clock distribution network design with zero asymptotic power dissipation for the GHz frequency range is proposed. Power dissipation and clock skew of the new global clock distribution network are analyzed. A simple experiment on a transmission line, as a scaled model of a clock distribution network, demonstrates a 97% reduction in power dissipation.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121717512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
RF interconnect for multi-Gbit/sec board-level clock distribution 用于多gbit /sec板级时钟分配的射频互连
Woonghwan Ryu, Hyungsoo Kim, Seungyoung Ahn, Namhoon Kim, Baekkyu Choi, Joungho Kim
{"title":"RF interconnect for multi-Gbit/sec board-level clock distribution","authors":"Woonghwan Ryu, Hyungsoo Kim, Seungyoung Ahn, Namhoon Kim, Baekkyu Choi, Joungho Kim","doi":"10.1109/EPEP.1999.819188","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819188","url":null,"abstract":"We newly propose a multi-Gbit/sec clock distribution scheme to achieve minimized skew and jitter using RF interconnects. The proposed RF clock distribution scheme has successfully demonstrated less than 22 ps skew and less than 3 ps jitter at 2 GHz.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125663574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and performance evaluation of chip capacitors on microprocessor packaging 微处理器封装上芯片电容器的设计和性能评估
T. Yew, Yuan-liang Li, C. Chung, D. Figueroa
{"title":"Design and performance evaluation of chip capacitors on microprocessor packaging","authors":"T. Yew, Yuan-liang Li, C. Chung, D. Figueroa","doi":"10.1109/EPEP.1999.819220","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819220","url":null,"abstract":"This paper describes the different chip capacitor placement design on Intel's latest Celeron CPU package. The evaluation of its effectiveness in the power delivery network and final impact on CPU performance are also discussed.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125788034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Electrical performance of buried capacitors in multi-layered PCBs 多层pcb中埋地电容器的电性能
A. Madou, L. Martens
{"title":"Electrical performance of buried capacitors in multi-layered PCBs","authors":"A. Madou, L. Martens","doi":"10.1109/EPEP.1999.819204","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819204","url":null,"abstract":"This paper describes the design of prototype buried capacitors and presents some measurement and modeling results performed on these test structures. This work is being carried out under a European Brite-EuRAM funded project, COMPRISE. The objective of this project is to develop new materials and manufacturing processes to embed passive components (R, L, and C) within printed wiring structures fabricated from laminate materials.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129819010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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